From e809e8957171e86689a360efc76111155542eba2 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 8 Mar 2016 13:01:52 +0100 Subject: [PATCH 01/11] pipistrello: adhere to pmod interface type 2 layout --- artiq/gateware/targets/pipistrello.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index 80985c04a..95dae2b29 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -196,10 +196,10 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd pmod = self.platform.request("pmod", 0) spi_pins = Module() - spi_pins.clk = pmod.d[0] + spi_pins.cs_n = pmod.d[0] spi_pins.mosi = pmod.d[1] spi_pins.miso = pmod.d[2] - spi_pins.cs_n = pmod.d[3:] + spi_pins.clk = pmod.d[3] phy = spi.SPIMaster(spi_pins) self.submodules += phy self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels) From 2180c5af7c0a609137e75334f14b249bae2b7fed Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 8 Mar 2016 13:07:58 +0100 Subject: [PATCH 02/11] pipistrello: make pmod[4:8] available as ttls --- artiq/gateware/targets/pipistrello.py | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index 95dae2b29..31e5b4865 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -177,6 +177,15 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4)) + pmod = self.platform.request("pmod", 0) + + for i in range(4, 8): + phy = ttl_serdes_spartan6.Inout_4X(pmod.d[i], + self.rtio_crg.rtiox4_stb) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32, + ofifo_depth=32)) + self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) phy = ttl_simple.ClockGen(platform.request("ttl", 15)) @@ -194,7 +203,6 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd ofifo_depth=512, ififo_depth=4)) - pmod = self.platform.request("pmod", 0) spi_pins = Module() spi_pins.cs_n = pmod.d[0] spi_pins.mosi = pmod.d[1] @@ -204,7 +212,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd self.submodules += phy self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.Channel.from_phy( - phy, ofifo_depth=4, ififo_depth=4)) + phy, ofifo_depth=32, ififo_depth=32)) self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) From e23e91f8ac061da87ed2f80e6b6c592e421e9608 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 8 Mar 2016 13:13:33 +0100 Subject: [PATCH 03/11] doc: add pipistrello pmod ttl channels --- doc/manual/core_device.rst | 50 ++++++++++++++++++++++---------------- 1 file changed, 29 insertions(+), 21 deletions(-) diff --git a/doc/manual/core_device.rst b/doc/manual/core_device.rst index c53ccbe23..2f80365bd 100644 --- a/doc/manual/core_device.rst +++ b/doc/manual/core_device.rst @@ -99,27 +99,35 @@ The low-cost Pipistrello FPGA board can be used as a lower-cost but slower alter When plugged to an adapter, the NIST QC1 hardware can be used. The TTL lines are mapped to RTIO channels as follows: -+--------------+------------+------------+ -| RTIO channel | TTL line | Capability | -+==============+============+============+ -| 0 | PMT0 | Input | -+--------------+------------+------------+ -| 1 | PMT1 | Input | -+--------------+------------+------------+ -| 2-16 | TTL0-14 | Output | -+--------------+------------+------------+ -| 17 | EXT_LED | Output | -+--------------+------------+------------+ -| 18 | USER_LED_1 | Output | -+--------------+------------+------------+ -| 19 | USER_LED_2 | Output | -+--------------+------------+------------+ -| 20 | USER_LED_3 | Output | -+--------------+------------+------------+ -| 21 | USER_LED_4 | Output | -+--------------+------------+------------+ -| 22 | TTL15 | Clock | -+--------------+------------+------------+ ++--------------+------------+--------------+ +| RTIO channel | TTL line | Capability | ++==============+============+==============+ +| 0 | PMT0 | Input | ++--------------+------------+--------------+ +| 1 | PMT1 | Input | ++--------------+------------+--------------+ +| 2-16 | TTL0-14 | Output | ++--------------+------------+--------------+ +| 17 | EXT_LED | Output | ++--------------+------------+--------------+ +| 18 | USER_LED_1 | Output | ++--------------+------------+--------------+ +| 19 | USER_LED_2 | Output | ++--------------+------------+--------------+ +| 20 | USER_LED_3 | Output | ++--------------+------------+--------------+ +| 21 | USER_LED_4 | Output | ++--------------+------------+--------------+ +| 22 | PMOD_4 | Input+Output | ++--------------+------------+--------------+ +| 23 | PMOD_5 | Input+Output | ++--------------+------------+--------------+ +| 24 | PMOD_6 | Input+Output | ++--------------+------------+--------------+ +| 25 | PMOD_7 | Input+Output | ++--------------+------------+--------------+ +| 26 | TTL15 | Clock | ++--------------+------------+--------------+ The input only limitation on channels 0 and 1 comes from the QC-DAQ adapter. When the adapter is not used (and physically unplugged from the Pipistrello board), the corresponding pins on the Pipistrello can be used as outputs. Do not configure these channels as outputs when the adapter is plugged, as this would cause electrical contention. From 9898cb14db09e7efb6260dd3a94a0470c9943f01 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 8 Mar 2016 13:18:55 +0100 Subject: [PATCH 04/11] doc: add pipistrello spi bus --- doc/manual/core_device.rst | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/doc/manual/core_device.rst b/doc/manual/core_device.rst index 2f80365bd..db2e69e91 100644 --- a/doc/manual/core_device.rst +++ b/doc/manual/core_device.rst @@ -132,3 +132,12 @@ When plugged to an adapter, the NIST QC1 hardware can be used. The TTL lines are The input only limitation on channels 0 and 1 comes from the QC-DAQ adapter. When the adapter is not used (and physically unplugged from the Pipistrello board), the corresponding pins on the Pipistrello can be used as outputs. Do not configure these channels as outputs when the adapter is plugged, as this would cause electrical contention. The board can accept an external RTIO clock connected to PMT2. If the DDS box does not drive the PMT2 pair, use XTRIG and patch the XTRIG transceiver output on the adapter board onto C:15 disconnecting PMT2. + +The board has one RTIO SPI bus on the PMOD connector, compliant to PMOD +Interface Type 2 (SPI) and 2A (expanded SPI): + ++--------------+--------+--------+--------+--------+ +| RTIO channel | CS_N | MOSI | MISO | CLK | ++==============+========+========+========+========+ +| 28 | PMOD_0 | PMOD_1 | PMOD_2 | PMOD_3 | ++--------------+--------+--------+--------+--------+ From 40c1cde2e2c0652613c9cd69cc1a380a70ef2d2a Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 8 Mar 2016 13:28:32 +0100 Subject: [PATCH 05/11] doc: kc705.clock: add spi bus mappings (closes #321) --- doc/manual/core_device.rst | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/doc/manual/core_device.rst b/doc/manual/core_device.rst index db2e69e91..ec372418e 100644 --- a/doc/manual/core_device.rst +++ b/doc/manual/core_device.rst @@ -75,6 +75,20 @@ With the CLOCK hardware, the TTL lines are mapped as follows: | 21 | LA32_P | Clock | +--------------------+-----------------------+--------------+ +The board has RTIO SPI buses mapped as follows: + ++--------------+-------------+-------------+-----------+------------+ +| RTIO channel | CS_N | MOSI | MISO | CLK | ++==============+=============+=============+===========+============+ +| 22 | AMS101_CS_N | AMS101_MOSI | | AMS101_CLK | ++--------------+-------------+-------------+-----------+------------+ +| 23 | SPI0_CS_N | SPI0_MOSI | SPI0_MISO | SPI0_CLK | ++--------------+-------------+-------------+-----------+------------+ +| 24 | SPI1_CS_N | SPI1_MOSI | SPI1_MISO | SPI1_CLK | ++--------------+-------------+-------------+-----------+------------+ +| 25 | SPI2_CS_N | SPI2_MOSI | SPI2_MISO | SPI2_CLK | ++--------------+-------------+-------------+-----------+------------+ + NIST QC2 ++++++++ From 104d641c59c575e3d1295f7b88cf666c3a47a239 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 8 Mar 2016 13:30:05 +0100 Subject: [PATCH 06/11] pipistrello: move the spi channel like kc705 --- artiq/gateware/targets/pipistrello.py | 22 +++++++++++----------- doc/manual/core_device.rst | 2 +- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index 31e5b4865..b06eef461 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -192,17 +192,6 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels) - self.config["DDS_CHANNEL_COUNT"] = 8 - self.config["DDS_AD9858"] = True - dds_pins = platform.request("dds") - self.comb += dds_pins.p.eq(0) - phy = dds.AD9858(dds_pins, 8) - self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, - ofifo_depth=512, - ififo_depth=4)) - spi_pins = Module() spi_pins.cs_n = pmod.d[0] spi_pins.mosi = pmod.d[1] @@ -214,6 +203,17 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd rtio_channels.append(rtio.Channel.from_phy( phy, ofifo_depth=32, ififo_depth=32)) + self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels) + self.config["DDS_CHANNEL_COUNT"] = 8 + self.config["DDS_AD9858"] = True + dds_pins = platform.request("dds") + self.comb += dds_pins.p.eq(0) + phy = dds.AD9858(dds_pins, 8) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy, + ofifo_depth=512, + ififo_depth=4)) + self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) diff --git a/doc/manual/core_device.rst b/doc/manual/core_device.rst index ec372418e..8a947dab6 100644 --- a/doc/manual/core_device.rst +++ b/doc/manual/core_device.rst @@ -153,5 +153,5 @@ Interface Type 2 (SPI) and 2A (expanded SPI): +--------------+--------+--------+--------+--------+ | RTIO channel | CS_N | MOSI | MISO | CLK | +==============+========+========+========+========+ -| 28 | PMOD_0 | PMOD_1 | PMOD_2 | PMOD_3 | +| 27 | PMOD_0 | PMOD_1 | PMOD_2 | PMOD_3 | +--------------+--------+--------+--------+--------+ From 9c11cda7dcb2289e7b8504781e829a232d3cc7ef Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 8 Mar 2016 13:52:52 +0100 Subject: [PATCH 07/11] pipistrello: use ttl_simple for pmod[4:8] --- artiq/gateware/targets/pipistrello.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index b06eef461..bf3e3f8d7 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -180,8 +180,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd pmod = self.platform.request("pmod", 0) for i in range(4, 8): - phy = ttl_serdes_spartan6.Inout_4X(pmod.d[i], - self.rtio_crg.rtiox4_stb) + phy = ttl_simple.Inout(pmod.d[i]) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32, ofifo_depth=32)) From 00d4775da5ce7b2ea9d3679d83d37c2c2eabf9df Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 8 Mar 2016 15:40:12 +0100 Subject: [PATCH 08/11] pipistrello: shrink fifos a bit (may make ise happier) --- artiq/gateware/targets/pipistrello.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index bf3e3f8d7..f63cec55a 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -151,7 +151,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i), self.rtio_crg.rtiox4_stb) self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512, + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=256, ofifo_depth=4)) # the last TTL is used for ClockGen @@ -166,7 +166,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd phy = ttl_simple.Output(platform.request("ttl", i)) self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=256)) + rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=128)) phy = ttl_simple.Output(platform.request("ext_led", 0)) self.submodules += phy @@ -182,8 +182,8 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd for i in range(4, 8): phy = ttl_simple.Inout(pmod.d[i]) self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32, - ofifo_depth=32)) + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=8, + ofifo_depth=8)) self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) @@ -200,7 +200,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd self.submodules += phy self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.Channel.from_phy( - phy, ofifo_depth=32, ififo_depth=32)) + phy, ofifo_depth=8, ififo_depth=8)) self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels) self.config["DDS_CHANNEL_COUNT"] = 8 @@ -210,7 +210,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd phy = dds.AD9858(dds_pins, 8) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, - ofifo_depth=512, + ofifo_depth=256, ififo_depth=4)) self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) From 41ca223c456807d2c7a03ca17b7587d3dde08c75 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 8 Mar 2016 15:53:27 +0100 Subject: [PATCH 09/11] gui: ignore only unmodified wheelevents --- artiq/gui/tools.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/gui/tools.py b/artiq/gui/tools.py index 97964bf4c..7782165d6 100644 --- a/artiq/gui/tools.py +++ b/artiq/gui/tools.py @@ -17,11 +17,11 @@ def log_level_to_name(level): class _WheelFilter(QtCore.QObject): def eventFilter(self, obj, event): - if event.type() == QtCore.QEvent.Wheel: + if (event.type() == QtCore.QEvent.Wheel and + event.modifiers() == QtCore.Qt.NoModifier): event.ignore() return True - else: - return False + return False def disable_scroll_wheel(widget): From c08881de5d8050bd07a2395f5086c50fb2e95cec Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 8 Mar 2016 16:12:38 +0100 Subject: [PATCH 10/11] gui: don't scroll experiment editor on modified wheel (closes #303) If you try to target e.g. spinbox with a ctrl- or shift-wheel to change the value and you don't aim well, the tree widget will scroll. We already have tree scroll on unmodified wheel. Let's have the modified wheel events exclusively target the smaller widgets. --- artiq/gui/experiments.py | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/artiq/gui/experiments.py b/artiq/gui/experiments.py index aeb4cfff4..0cb11bbe1 100644 --- a/artiq/gui/experiments.py +++ b/artiq/gui/experiments.py @@ -18,6 +18,15 @@ logger = logging.getLogger(__name__) # 2. file:@ +class _WheelFilter(QtCore.QObject): + def eventFilter(self, obj, event): + if (event.type() == QtCore.QEvent.Wheel and + event.modifiers() != QtCore.Qt.NoModifier): + event.ignore() + return True + return False + + class _ArgumentEditor(QtWidgets.QTreeWidget): def __init__(self, manager, dock, expurl): self.manager = manager @@ -38,6 +47,8 @@ class _ArgumentEditor(QtWidgets.QTreeWidget): self.setHorizontalScrollMode(QtWidgets.QAbstractItemView.ScrollPerPixel) self.setVerticalScrollMode(QtWidgets.QAbstractItemView.ScrollPerPixel) + self.viewport().installEventFilter(_WheelFilter(self.viewport())) + self._groups = dict() self._arg_to_entry_widgetitem = dict() From a8fe3f50c35b9abb13b5b4bd66a9cc505b9dadaf Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 8 Mar 2016 16:17:37 +0100 Subject: [PATCH 11/11] pipistrello: grow fifos a bit (may make ise happier) --- artiq/gateware/targets/pipistrello.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index f63cec55a..8cd6b22ee 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -151,7 +151,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i), self.rtio_crg.rtiox4_stb) self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=256, + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512, ofifo_depth=4)) # the last TTL is used for ClockGen @@ -166,7 +166,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd phy = ttl_simple.Output(platform.request("ttl", i)) self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=128)) + rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=256)) phy = ttl_simple.Output(platform.request("ext_led", 0)) self.submodules += phy @@ -182,8 +182,8 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd for i in range(4, 8): phy = ttl_simple.Inout(pmod.d[i]) self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=8, - ofifo_depth=8)) + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128, + ofifo_depth=128)) self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) @@ -200,7 +200,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd self.submodules += phy self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.Channel.from_phy( - phy, ofifo_depth=8, ififo_depth=8)) + phy, ofifo_depth=128, ififo_depth=128)) self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels) self.config["DDS_CHANNEL_COUNT"] = 8 @@ -210,7 +210,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd phy = dds.AD9858(dds_pins, 8) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, - ofifo_depth=256, + ofifo_depth=512, ififo_depth=4)) self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)