From 27160f5912609dad9bee52d5fd79e913ba63ba3a Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 29 Nov 2016 15:28:10 +0100 Subject: [PATCH] phaser: make sysref input only for timing --- artiq/gateware/targets/phaser.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/targets/phaser.py b/artiq/gateware/targets/phaser.py index 9d37d2419..6208ef5c6 100755 --- a/artiq/gateware/targets/phaser.py +++ b/artiq/gateware/targets/phaser.py @@ -22,7 +22,8 @@ from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict from misoc.integration.builder import builder_args, builder_argdict from artiq.gateware.soc import AMPSoC, build_artiq_soc -from artiq.gateware import rtio, phaser +from artiq.gateware import rtio +from artiq.gateware.phaser import fmc_adapter_io from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series, sawg) from artiq import __version__ as artiq_version @@ -172,7 +173,7 @@ class Phaser(MiniSoC, AMPSoC): ]) platform = self.platform - platform.add_extension(phaser.fmc_adapter_io) + platform.add_extension(fmc_adapter_io) self.submodules.leds = gpio.GPIOOut(Cat( platform.request("user_led", 0), @@ -201,7 +202,7 @@ class Phaser(MiniSoC, AMPSoC): rtio_channels.append(rtio.Channel.from_phy(phy)) sysref_pads = platform.request("ad9154_sysref") - phy = ttl_serdes_7series.Inout_8X(sysref_pads.p, sysref_pads.n) + phy = ttl_serdes_7series.Input_8X(sysref_pads.p, sysref_pads.n) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32, ofifo_depth=2))