occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

Generate more compact ARTIQ IR for else-less if.

This commit is contained in:
whitequark 2015-07-18 07:49:27 +03:00
parent e96bc3c36c
commit 255ffec483
1 changed files with 11 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
artiq/compiler/transforms/ir_generator.py
View File

@ -238,6 +238,7 @@ class IRGenerator(algorithm.Visitor):
self.current_block = if_true
self.visit(node.body)
if any(node.orelse):
if_false = self.add_block()
self.current_block = if_false
self.visit(node.orelse)
@ -246,9 +247,13 @@ class IRGenerator(algorithm.Visitor):
self.current_block = tail
if not if_true.is_terminated():
if_true.append(ir.Branch(tail))
if any(node.orelse):
if not if_false.is_terminated():
if_false.append(ir.Branch(tail))
head.append(ir.BranchIf(cond, if_true, if_false))
else:
head.append(ir.BranchIf(cond, if_true, tail))
def visit_While(self, node):
try: