From 2100a8b1f1b3ab281bac1e8450d61df1b57d30a2 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 5 Jan 2019 12:25:30 +0800 Subject: [PATCH] sayma_amc: more fighting with vivado timing analyzer --- artiq/gateware/targets/sayma_amc.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index fe56269c8..3561eb7b6 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -326,13 +326,19 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon): gth = self.drtio_transceiver.gths[0] platform.add_period_constraint(gth.txoutclk, rtio_clk_period/2) platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) + self.drtio_transceiver.cd_rtio.clk.attr.add("keep") platform.add_false_path_constraints( self.crg.cd_sys.clk, - gth.txoutclk, gth.rxoutclk) + self.drtio_transceiver.cd_rtio.clk, gth.rxoutclk) + platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk) for gth in self.drtio_transceiver.gths[1:]: platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( self.crg.cd_sys.clk, gth.rxoutclk) + platform.add_false_path_constraints( + self.drtio_transceiver.cd_rtio.clk, gth.rxoutclk) + platform.add_false_path_constraints(self.ad9154_crg.cd_jesd.clk, + self.drtio_transceiver.cd_rtio.clk) rtio_channels = [] for i in range(4):