From 7d4297b9bb97b6ce9a7aa9735b2ebce74bf4e446 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 24 Nov 2016 10:18:27 +0800 Subject: [PATCH 1/3] pc_rpc: use ProactorEventLoop on Windows (#627) --- artiq/protocols/pc_rpc.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/artiq/protocols/pc_rpc.py b/artiq/protocols/pc_rpc.py index bf3f1c12b..f2acd9bfc 100644 --- a/artiq/protocols/pc_rpc.py +++ b/artiq/protocols/pc_rpc.py @@ -11,6 +11,7 @@ client passes a list as a parameter of an RPC method, and that method client's list. """ +import os import socket import asyncio import threading @@ -592,7 +593,11 @@ def simple_server_loop(targets, host, port, description=None): See ``Server`` for a description of the parameters. """ - loop = asyncio.get_event_loop() + if os.name == "nt": + loop = asyncio.ProactorEventLoop() + asyncio.set_event_loop(loop) + else: + loop = asyncio.get_event_loop() try: server = Server(targets, description, True) loop.run_until_complete(server.start(host, port)) From d0a55e5c9bcc062b91a54ff51bc963ff913bfa4a Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Thu, 24 Nov 2016 14:24:12 +0100 Subject: [PATCH 2/3] RELEASE_NOTES: int(a, width=b) removal, use int32/64 --- RELEASE_NOTES.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/RELEASE_NOTES.rst b/RELEASE_NOTES.rst index 635bb607d..b2f8e1d8a 100644 --- a/RELEASE_NOTES.rst +++ b/RELEASE_NOTES.rst @@ -22,6 +22,7 @@ Release notes * The Pipistrello port now has exclusively TTLs. * The DDS class names and setup options have changed, this requires an update of the device database. +* ``int(a, width=b)`` has been removed. Use ``int32(a)`` and ``int64(a)``. 2.0 From 95c885b580a8d09860c39fe54d82a0a1ab915ed9 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Sat, 1 Oct 2016 01:26:49 +0200 Subject: [PATCH 3/3] rtio: support differential ttl --- artiq/gateware/rtio/phy/ttl_serdes_7series.py | 32 +++++++++++++------ 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/artiq/gateware/rtio/phy/ttl_serdes_7series.py b/artiq/gateware/rtio/phy/ttl_serdes_7series.py index b8c759ce9..018762984 100644 --- a/artiq/gateware/rtio/phy/ttl_serdes_7series.py +++ b/artiq/gateware/rtio/phy/ttl_serdes_7series.py @@ -4,7 +4,7 @@ from artiq.gateware.rtio.phy import ttl_serdes_generic class _OSERDESE2_8X(Module): - def __init__(self, pad): + def __init__(self, pad, pad_n=None): self.o = Signal(8) self.t_in = Signal() self.t_out = Signal() @@ -12,20 +12,27 @@ class _OSERDESE2_8X(Module): # # # o = self.o + pad_o = Signal() self.specials += Instance("OSERDESE2", p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF", p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1, - o_OQ=pad, o_TQ=self.t_out, + o_OQ=pad_o, o_TQ=self.t_out, i_CLK=ClockSignal("rtiox4"), i_CLKDIV=ClockSignal("rio_phy"), i_D1=o[0], i_D2=o[1], i_D3=o[2], i_D4=o[3], i_D5=o[4], i_D6=o[5], i_D7=o[6], i_D8=o[7], i_TCE=1, i_OCE=1, i_RST=0, i_T1=self.t_in) + if pad_n is None: + self.comb += pad.eq(pad_o) + else: + self.specials += Instance("OBUFDS", + i_I=pad_o, + o_O=pad, o_OB=pad_n) class _IOSERDESE2_8X(Module): - def __init__(self, pad): + def __init__(self, pad, pad_n=None): self.o = Signal(8) self.i = Signal(8) self.oe = Signal() @@ -47,9 +54,14 @@ class _IOSERDESE2_8X(Module): i_CLKDIV=ClockSignal("rio_phy")) oserdes = _OSERDESE2_8X(pad_o) self.submodules += oserdes - self.specials += Instance("IOBUF", - i_I=pad_o, o_O=pad_i, i_T=oserdes.t_out, - io_IO=pad) + if pad_n is None: + self.specials += Instance("IOBUF", + i_I=pad_o, o_O=pad_i, i_T=oserdes.t_out, + io_IO=pad) + else: + self.specials += Instance("IOBUFDS", + i_I=pad_o, o_O=pad_i, i_T=oserdes.t_out, + io_IO=pad, io_IOB=pad_n) self.comb += [ oserdes.t_in.eq(~self.oe), oserdes.o.eq(self.o) @@ -57,14 +69,14 @@ class _IOSERDESE2_8X(Module): class Output_8X(ttl_serdes_generic.Output): - def __init__(self, pad): - serdes = _OSERDESE2_8X(pad) + def __init__(self, pad, pad_n=None): + serdes = _OSERDESE2_8X(pad, pad_n) self.submodules += serdes ttl_serdes_generic.Output.__init__(self, serdes) class Inout_8X(ttl_serdes_generic.Inout): - def __init__(self, pad): - serdes = _IOSERDESE2_8X(pad) + def __init__(self, pad, pad_n=None): + serdes = _IOSERDESE2_8X(pad, pad_n) self.submodules += serdes ttl_serdes_generic.Inout.__init__(self, serdes)