diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py
index 7a175f8fd..896a00ae7 100755
--- a/artiq/gateware/targets/sayma_amc.py
+++ b/artiq/gateware/targets/sayma_amc.py
@@ -174,7 +174,7 @@ class Standalone(MiniSoC, AMPSoC):
         self.submodules.serwb_phy_amc = serwb_phy_amc
         self.csr_devices.append("serwb_phy_amc")
 
-        serwb_core = serwb.core.SERWBCore(serwb_phy_amc, int(self.clk_freq), mode="slave", with_scrambling=False)
+        serwb_core = serwb.core.SERWBCore(serwb_phy_amc, int(self.clk_freq), mode="slave", with_scrambling=True)
         self.submodules += serwb_core
         self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
 
diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py
index efd491b5d..22e2580fb 100755
--- a/artiq/gateware/targets/sayma_rtm.py
+++ b/artiq/gateware/targets/sayma_rtm.py
@@ -161,7 +161,7 @@ class SaymaRTM(Module):
         self.comb += self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.refclk)
         csr_devices.append("serwb_phy_rtm")
 
-        serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master", with_scrambling=False)
+        serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master", with_scrambling=True)
         self.submodules += serwb_core
 
         # process CSR devices and connect them to serwb