From 19498e59f9d259edd67a4e0cbbfa4e71318c222b Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Wed, 29 Nov 2017 18:18:41 +0800
Subject: [PATCH] libboard: fix JESD reset release

---
 artiq/firmware/libboard/ad9154.rs | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/artiq/firmware/libboard/ad9154.rs b/artiq/firmware/libboard/ad9154.rs
index db74f924b..1a1b8698f 100644
--- a/artiq/firmware/libboard/ad9154.rs
+++ b/artiq/firmware/libboard/ad9154.rs
@@ -35,9 +35,9 @@ fn read(addr: u16) -> u8 {
     }
 }
 
-fn jesd_reset(dacno: u8, rst: bool) {
+fn jesd_unreset() {
     unsafe {
-        (csr::AD9154[dacno as usize].jesd_jreset_write)(if rst {1} else {0})
+        csr::ad9154_crg::jreset_write(0)
     }
 }
 
@@ -425,7 +425,7 @@ fn cfg(dacno: u8) -> Result<(), &'static str> {
     spi_setup(dacno);
     // Release the JESD clock domain reset late, as we need to
     // set up clock chips before.
-    jesd_reset(dacno, false);
+    jesd_unreset();
 
     jesd_enable(dacno, false);
     jesd_prbs(dacno, false);