gateware: share RTIOClockMultiplier and fix_serdes_timing_path (#1760)

artiq/gateware/rtio/xilinx_clocking.py

@@ -0,0 +1,45 @@
+from migen import *
+from migen.genlib.cdc import MultiReg
+from misoc.interconnect.csr import *
+
+
+class RTIOClockMultiplier(Module, AutoCSR):
+    def __init__(self, rtio_clk_freq):
+        self.pll_reset = CSRStorage(reset=1)
+        self.pll_locked = CSRStatus()
+        self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
+
+        # See "Global Clock Network Deskew Using Two BUFGs" in ug472.
+        clkfbout = Signal()
+        clkfbin = Signal()
+        rtiox4_clk = Signal()
+        pll_locked = Signal()
+        self.specials += [
+            Instance("MMCME2_BASE",
+                     p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
+                     i_CLKIN1=ClockSignal("rtio"),
+                     i_RST=self.pll_reset.storage,
+                     o_LOCKED=pll_locked,
+
+                     p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
+
+                     o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbin,
+
+                     p_CLKOUT0_DIVIDE_F=2.0, o_CLKOUT0=rtiox4_clk,
+                     ),
+            Instance("BUFG", i_I=clkfbout, o_O=clkfbin),
+            Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
+
+            MultiReg(pll_locked, self.pll_locked.status)
+        ]
+
+
+def fix_serdes_timing_path(platform):
+    # ignore timing of path from OSERDESE2 through the pad to ISERDESE2
+    platform.add_platform_command(
+        "set_false_path -quiet "
+        "-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
+            "-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
+        "-to [get_pins -filter {{REF_PIN_NAME == D}} "
+            "-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
+    )

artiq/gateware/targets/kasli.py

@@ -17,6 +17,7 @@ from misoc.integration.builder import builder_args, builder_argdict
 from artiq.gateware.amp import AMPSoC
 from artiq.gateware import rtio
 from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, edge_counter
+from artiq.gateware.rtio.xilinx_clocking import RTIOClockMultiplier, fix_serdes_timing_path
 from artiq.gateware import eem
 from artiq.gateware.drtio.transceiver import gtp_7series
 from artiq.gateware.drtio.siphaser import SiPhaser7Series
@@ -94,17 +95,6 @@ class SMAClkinForward(Module):
         ]
 
 
-def fix_serdes_timing_path(platform):
-    # ignore timing of path from OSERDESE2 through the pad to ISERDESE2
-    platform.add_platform_command(
-        "set_false_path -quiet "
-        "-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
-            "-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
-        "-to [get_pins -filter {{REF_PIN_NAME == D}} "
-            "-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
-    )
-
-
 class StandaloneBase(MiniSoC, AMPSoC):
     mem_map = {
         "cri_con":       0x10000000,
@@ -255,37 +245,6 @@ class SUServo(StandaloneBase):
             pads.clkout, self.crg.cd_sys.clk)
 
 
-class _RTIOClockMultiplier(Module, AutoCSR):
-    def __init__(self, rtio_clk_freq):
-        self.pll_reset = CSRStorage(reset=1)
-        self.pll_locked = CSRStatus()
-        self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
-
-        # See "Global Clock Network Deskew Using Two BUFGs" in ug472.
-        clkfbout = Signal()
-        clkfbin = Signal()
-        rtiox4_clk = Signal()
-        pll_locked = Signal()
-        self.specials += [
-            Instance("MMCME2_BASE",
-                p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
-                i_CLKIN1=ClockSignal("rtio"),
-                i_RST=self.pll_reset.storage,
-                o_LOCKED=pll_locked,
-
-                p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
-
-                o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbin,
-
-                p_CLKOUT0_DIVIDE_F=2.0, o_CLKOUT0=rtiox4_clk,
-            ),
-            Instance("BUFG", i_I=clkfbout, o_O=clkfbin),
-            Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
-
-            MultiReg(pll_locked, self.pll_locked.status)
-        ]
-
-
 class MasterBase(MiniSoC, AMPSoC):
     mem_map = {
         "cri_con":       0x10000000,
@@ -400,7 +359,7 @@ class MasterBase(MiniSoC, AMPSoC):
             platform.add_false_path_constraints(
                 self.crg.cd_sys.clk, gtp.rxoutclk)
 
-        self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
+        self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
         self.csr_devices.append("rtio_crg")
         fix_serdes_timing_path(platform)
 
@@ -627,7 +586,7 @@ class SatelliteBase(BaseSoC):
             platform.add_false_path_constraints(
                 self.crg.cd_sys.clk, gtp.rxoutclk)
 
-        self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
+        self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
         self.csr_devices.append("rtio_crg")
         fix_serdes_timing_path(platform)
 

artiq/gateware/targets/kc705.py

@@ -17,6 +17,7 @@ from misoc.integration.builder import builder_args, builder_argdict
 from artiq.gateware.amp import AMPSoC
 from artiq.gateware import rtio, nist_clock, nist_qc2
 from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
+from artiq.gateware.rtio.xilinx_clocking import RTIOClockMultiplier, fix_serdes_timing_path
 from artiq.gateware.drtio.transceiver import gtx_7series
 from artiq.gateware.drtio.siphaser import SiPhaser7Series
 from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
@@ -82,48 +83,6 @@ class _RTIOCRG(Module, AutoCSR):
         ]
 
 
-class _RTIOClockMultiplier(Module, AutoCSR):
-    def __init__(self, rtio_clk_freq):
-        self.pll_reset = CSRStorage(reset=1)
-        self.pll_locked = CSRStatus()
-        self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
-
-        # See "Global Clock Network Deskew Using Two BUFGs" in ug472.
-        clkfbout = Signal()
-        clkfbin = Signal()
-        rtiox4_clk = Signal()
-        pll_locked = Signal()
-        self.specials += [
-            Instance("MMCME2_BASE",
-                p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
-                i_CLKIN1=ClockSignal("rtio"),
-                i_RST=self.pll_reset.storage,
-                o_LOCKED=pll_locked,
-
-                p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
-
-                o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbin,
-
-                p_CLKOUT0_DIVIDE_F=2.0, o_CLKOUT0=rtiox4_clk,
-            ),
-            Instance("BUFG", i_I=clkfbout, o_O=clkfbin),
-            Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
-
-            MultiReg(pll_locked, self.pll_locked.status)
-        ]
-
-
-def fix_serdes_timing_path(platform):
-    # ignore timing of path from OSERDESE2 through the pad to ISERDESE2
-    platform.add_platform_command(
-        "set_false_path -quiet "
-        "-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
-            "-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
-        "-to [get_pins -filter {{REF_PIN_NAME == D}} "
-            "-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
-    )
-
-
 # The default voltage for these signals on KC705 is 2.5V, and the Migen platform
 # follows this default. But since the SMAs are on the same bank as the DDS,
 # which is set to 3.3V by reprogramming the KC705 power ICs, we need to
@@ -349,7 +308,7 @@ class _MasterBase(MiniSoC, AMPSoC):
             platform.add_false_path_constraints(
                 self.crg.cd_sys.clk, gtx0.txoutclk, gtx.rxoutclk)
 
-        self.submodules.rtio_crg = _RTIOClockMultiplier(self.drtio_transceiver.rtio_clk_freq)
+        self.submodules.rtio_crg = RTIOClockMultiplier(self.drtio_transceiver.rtio_clk_freq)
         self.csr_devices.append("rtio_crg")
         fix_serdes_timing_path(platform)
 
@@ -498,7 +457,7 @@ class _SatelliteBase(BaseSoC):
             platform.add_false_path_constraints(
                 self.crg.cd_sys.clk, gtx.rxoutclk)
 
-        self.submodules.rtio_crg = _RTIOClockMultiplier(self.drtio_transceiver.rtio_clk_freq)
+        self.submodules.rtio_crg = RTIOClockMultiplier(self.drtio_transceiver.rtio_clk_freq)
         self.csr_devices.append("rtio_crg")
         fix_serdes_timing_path(platform)
 

artiq/gateware/targets/sayma_rtm.py

@@ -18,6 +18,7 @@ from misoc.integration.builder import Builder, builder_args, builder_argdict
 from artiq.gateware import rtio
 from artiq.gateware import jesd204_tools
 from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series
+from artiq.gateware.rtio.xilinx_clocking import RTIOClockMultiplier, fix_serdes_timing_path
 from artiq.gateware.drtio.transceiver import gtp_7series
 from artiq.gateware.drtio.siphaser import SiPhaser7Series
 from artiq.gateware.drtio.wrpll import WRPLL, DDMTDSamplerGTP
@@ -27,48 +28,6 @@ from artiq.build_soc import add_identifier
 from artiq import __artiq_dir__ as artiq_dir
 
 
-def fix_serdes_timing_path(platform):
-    # ignore timing of path from OSERDESE2 through the pad to ISERDESE2
-    platform.add_platform_command(
-        "set_false_path -quiet "
-        "-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
-            "-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
-        "-to [get_pins -filter {{REF_PIN_NAME == D}} "
-            "-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
-    )
-
-
-class _RTIOClockMultiplier(Module, AutoCSR):
-    def __init__(self, rtio_clk_freq):
-        self.pll_reset = CSRStorage(reset=1)
-        self.pll_locked = CSRStatus()
-        self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
-
-        # See "Global Clock Network Deskew Using Two BUFGs" in ug472.
-        clkfbout = Signal()
-        clkfbin = Signal()
-        rtiox4_clk = Signal()
-        pll_locked = Signal()
-        self.specials += [
-            Instance("MMCME2_BASE",
-                p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
-                i_CLKIN1=ClockSignal("rtio"),
-                i_RST=self.pll_reset.storage,
-                o_LOCKED=pll_locked,
-
-                p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
-
-                o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbin,
-
-                p_CLKOUT0_DIVIDE_F=2.0, o_CLKOUT0=rtiox4_clk,
-            ),
-            Instance("BUFG", i_I=clkfbout, o_O=clkfbin),
-            Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
-
-            MultiReg(pll_locked, self.pll_locked.status)
-        ]
-
-
 class _SatelliteBase(BaseSoC):
     mem_map = {
         "drtioaux": 0x50000000,
@@ -178,7 +137,7 @@ class _SatelliteBase(BaseSoC):
             self.crg.cd_sys.clk,
             gtp.txoutclk, gtp.rxoutclk)
 
-        self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
+        self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
         self.csr_devices.append("rtio_crg")
         fix_serdes_timing_path(platform)