occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

coreanalyzer: add WB stb signal

This commit is contained in:
Robert Jördens 2017-02-18 14:53:10 +01:00
parent 039ced6637
commit 1573ff5fc1
1 changed files with 7 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
artiq/coredevice/analyzer.py
View File

@ -240,12 +240,15 @@ class DDSHandler:
self._decode_ad9914_write(message) self._decode_ad9914_write(message)
class WishboneHandlerMixin: class WishboneHandler:
def __init__(self, read_bit): def __init__(self, vcd_manager, name, read_bit):
self._reads = [] self._reads = []
self._read_bit = read_bit self._read_bit = read_bit
self.stb = vcd_manager.get_channel("{}/{}".format(name, "stb"), 1)
def process_message(self, message): def process_message(self, message):
self.stb.set_value("1")
self.stb.set_value("0")
if isinstance(message, OutputMessage): if isinstance(message, OutputMessage):
logger.debug("Wishbone out @%d adr=0x%02x data=0x%08x", logger.debug("Wishbone out @%d adr=0x%02x data=0x%08x",
message.timestamp, message.address, message.data) message.timestamp, message.address, message.data)
@ -270,11 +273,11 @@ class WishboneHandlerMixin:
raise NotImplementedError raise NotImplementedError
class SPIMasterHandler(WishboneHandlerMixin): class SPIMasterHandler(WishboneHandler):
def __init__(self, vcd_manager, name): def __init__(self, vcd_manager, name):
super().__init__(read_bit=0b100)
self.channels = {} self.channels = {}
with vcd_manager.scope("spi/{}".format(name)): with vcd_manager.scope("spi/{}".format(name)):
super().__init__(vcd_manager, name, read_bit=0b100)
for reg_name, reg_width in [ for reg_name, reg_width in [
("config", 32), ("chip_select", 16), ("config", 32), ("chip_select", 16),
("write_length", 8), ("read_length", 8), ("write_length", 8), ("read_length", 8),