From 150a02117cd619570b7a69fd95daf46e42f86262 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Mon, 9 Dec 2019 19:47:50 +0800
Subject: [PATCH] sayma_rtm: drive clk_src_ext_sel

---
 artiq/gateware/targets/sayma_rtm.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py
index 0c67ce437..018a4868d 100755
--- a/artiq/gateware/targets/sayma_rtm.py
+++ b/artiq/gateware/targets/sayma_rtm.py
@@ -205,6 +205,8 @@ class Satellite(_SatelliteBase):
 
         self.add_rtio(rtio_channels)
 
+        self.comb += platform.request("clk_src_ext_sel").eq(0)
+
         # HMC clock chip and DAC control
         self.comb += [
             platform.request("ad9154_rst_n", 0).eq(1),