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artiq
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bootloader: add rv32 exception handler 

Signed-off-by: occheung <dc@m-labs.hk>
This commit is contained in:
occheung 2021-07-15 15:58:13 +08:00
parent 46102ee737
commit 13032272fd
2 changed files with 8 additions and 3 deletions
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1
artiq/firmware/bootloader/Cargo.toml
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@ -17,3 +17,4 @@ byteorder = { version = "1.0", default-features = false }
crc = { version = "1.7", default-features = false }
board_misoc = { path = "../libboard_misoc", features = ["uart_console", "smoltcp"] }
smoltcp = { version = "0.6.0", default-features = false, features = ["ethernet", "proto-ipv4", "proto-ipv6", "socket-tcp"] }
riscv = { version = "0.6.0", features = ["inline-asm"] }

10
artiq/firmware/bootloader/main.rs
View File

@ -6,8 +6,9 @@ extern crate byteorder;
extern crate smoltcp;
#[macro_use]
extern crate board_misoc;
extern crate riscv;
use core::{ptr, slice};
use core::{ptr, slice, convert::TryFrom};
use crc::crc32;
use byteorder::{ByteOrder, BigEndian};
use board_misoc::{ident, cache, sdram, config, boot, mem as board_mem};
@ -16,6 +17,7 @@ use board_misoc::slave_fpga;
#[cfg(has_ethmac)]
use board_misoc::{clock, ethmac, net_settings};
use board_misoc::uart_console::Console;
use riscv::register::{mcause, mepc};
fn check_integrity() -> bool {
extern {
@ -517,8 +519,10 @@ pub extern fn main() -> i32 {
}
#[no_mangle]
pub extern fn exception(vect: u32, _regs: *const u32, pc: u32, ea: u32) {
panic!("exception {} at PC {:#08x}, EA {:#08x}", vect, pc, ea)
pub extern fn exception(_regs: *const u32) {
let pc = mepc::read();
let cause = mcause::read().cause();
panic!("{:?} at PC {:#08x}", cause, u32::try_from(pc).unwrap())
}
#[no_mangle]