diff --git a/artiq/gateware/jesd204_tools.py b/artiq/gateware/jesd204_tools.py
index cdba0f7f6..5e8c5e85d 100644
--- a/artiq/gateware/jesd204_tools.py
+++ b/artiq/gateware/jesd204_tools.py
@@ -37,6 +37,7 @@ class UltrascaleCRG(Module, AutoCSR):
         ]
 
         if use_rtio_clock:
+            self.cd_jesd.clk.attr.add("keep")
             self.comb += self.cd_jesd.clk.eq(ClockSignal("rtio"))
         else:
             self.specials += Instance("BUFG_GT", i_I=refclk2, o_O=self.cd_jesd.clk)