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artiq_flash: ignore RTM FPGA

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It has no flash connected, and attempting to detect it causes unnecessary program failure when the RTM is not present.
This commit is contained in:
Sebastien Bourdeauducq 2017-12-31 12:10:16 +08:00
parent 38ce1f1d5d
commit 100bda2582
1 changed files with 5 additions and 6 deletions
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11
artiq/frontend/artiq_flash.py
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@ -147,9 +147,8 @@ class ProgrammerSayma(Programmer):
"adapter_khz 5000", "adapter_khz 5000",
"transport select jtag", "transport select jtag",
"source [find cpld/xilinx-xc7.cfg]", # tap 0, pld 0
"set CHIP XCKU040", "set CHIP XCKU040",
"source [find cpld/xilinx-xcu.cfg]", # tap 1, pld 1 "source [find cpld/xilinx-xcu.cfg]",
"target create xcu.proxy testee -chain-position xcu.tap", "target create xcu.proxy testee -chain-position xcu.tap",
"set XILINX_USER1 0x02", "set XILINX_USER1 0x02",
@ -159,11 +158,11 @@ class ProgrammerSayma(Programmer):
] ]
self.init() self.init()
def load(self, bitfile, pld=1): def load(self, bitfile):
self.prog.append("pld load {} {{{}}}".format(pld, bitfile)) self.prog.append("pld load 0 {{{}}}".format(bitfile))
def proxy(self, proxy_bitfile, pld=1): def proxy(self, proxy_bitfile):
self.load(proxy_bitfile, pld) self.load(proxy_bitfile)
self.prog.append("reset halt") self.prog.append("reset halt")
def flash_binary(self, flashno, address, filename): def flash_binary(self, flashno, address, filename):