forked from M-Labs/artiq
test: fix hardware testbench trying to write to ARTIQ_ROOT
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parent
d5a7755584
commit
0e7e30d46e
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@ -5,6 +5,7 @@ import os
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import sys
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import unittest
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import logging
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from tempfile import TemporaryDirectory
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from artiq.master.databases import DeviceDB, DatasetDB
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from artiq.master.worker_db import DeviceManager, DatasetManager, DeviceError
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@ -19,9 +20,10 @@ logger = logging.getLogger(__name__)
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@unittest.skipUnless(artiq_root, "no ARTIQ_ROOT")
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class ExperimentCase(unittest.TestCase):
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def setUp(self):
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self.tempdir = TemporaryDirectory(prefix="artiq_hw_test")
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self.device_db = DeviceDB(os.path.join(artiq_root, "device_db.py"))
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self.dataset_db = DatasetDB(
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os.path.join(artiq_root, "dataset_db.mdb"))
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os.path.join(self.tempdir.name, "dataset_db.mdb"))
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self.device_mgr = DeviceManager(
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self.device_db, virtual_devices={"scheduler": DummyScheduler()})
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self.dataset_mgr = DatasetManager(self.dataset_db)
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@ -29,6 +31,7 @@ class ExperimentCase(unittest.TestCase):
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def tearDown(self):
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self.device_mgr.close_devices()
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self.dataset_db.close_db()
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self.tempdir.cleanup()
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def create(self, cls, *args, **kwargs):
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try:
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