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Gateware: kasli satellite WRPLL setup 

kasli: use enable_wrpll from json to switch from si5324 to si549
kasli: add wrpll
kasli: add wrpll interrupt
kasli: add clk_synth_se
kasli: add skewtester
kasli: add WRPLL_REF_CLK config for firmware
This commit is contained in:
morgan 2024-05-24 10:54:49 +08:00 committed by Sébastien Bourdeauducq
parent 1b0586e6a8
commit 0d78e65f7a
1 changed files with 30 additions and 12 deletions
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42
artiq/gateware/targets/kasli.py
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@ -26,6 +26,7 @@ from artiq.gateware.drtio.transceiver import gtp_7series, eem_serdes
from artiq.gateware.drtio.siphaser import SiPhaser7Series from artiq.gateware.drtio.siphaser import SiPhaser7Series
from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
from artiq.gateware.drtio import * from artiq.gateware.drtio import *
from artiq.gateware.wrpll import wrpll
from artiq.build_soc import * from artiq.build_soc import *
from artiq.coredevice import jsondesc from artiq.coredevice import jsondesc
@ -377,7 +378,7 @@ class SatelliteBase(BaseSoC, AMPSoC):
} }
mem_map.update(BaseSoC.mem_map) mem_map.update(BaseSoC.mem_map)
def __init__(self, rtio_clk_freq=125e6, enable_sata=False, *, gateware_identifier_str=None, hw_rev="v2.0", **kwargs): def __init__(self, rtio_clk_freq=125e6, enable_sata=False, with_wrpll=False, *, gateware_identifier_str=None, hw_rev="v2.0", **kwargs):
if hw_rev in ("v1.0", "v1.1"): if hw_rev in ("v1.0", "v1.1"):
cpu_bus_width = 32 cpu_bus_width = 32
else: else:
@ -505,17 +506,33 @@ class SatelliteBase(BaseSoC, AMPSoC):
rtio_clk_period = 1e9/rtio_clk_freq rtio_clk_period = 1e9/rtio_clk_freq
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
self.submodules.siphaser = SiPhaser7Series( if with_wrpll:
si5324_clkin=platform.request("cdr_clk") if platform.hw_rev == "v2.0" clk_synth = platform.request("cdr_clk_clean_fabric")
else platform.request("si5324_clkin"), clk_synth_se = Signal()
rx_synchronizer=self.rx_synchronizer, platform.add_period_constraint(clk_synth.p, 8.0)
ref_clk=self.crg.clk125_div2, ref_div2=True, self.specials += Instance("IBUFGDS", p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
rtio_clk_freq=rtio_clk_freq) self.submodules.wrpll = wrpll.WRPLL(
platform.add_false_path_constraints( platform=self.platform,
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) cd_ref=self.gt_drtio.cd_rtio_rx0,
self.csr_devices.append("siphaser") main_clk_se=clk_synth_se)
self.config["HAS_SI5324"] = None self.submodules.wrpll_skewtester = wrpll.SkewTester(self.rx_synchronizer)
self.config["SI5324_SOFT_RESET"] = None self.csr_devices.append("wrpll_skewtester")
self.csr_devices.append("wrpll")
self.interrupt_devices.append("wrpll")
self.config["HAS_SI549"] = None
self.config["WRPLL_REF_CLK"] = "GT_CDR"
else:
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("cdr_clk") if platform.hw_rev == "v2.0"
else platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer,
ref_clk=self.crg.clk125_div2, ref_div2=True,
rtio_clk_freq=rtio_clk_freq)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
gtp = self.gt_drtio.gtps[0] gtp = self.gt_drtio.gtps[0]
txout_buf = Signal() txout_buf = Signal()
@ -715,6 +732,7 @@ class GenericSatellite(SatelliteBase):
rtio_clk_freq=description["rtio_frequency"], rtio_clk_freq=description["rtio_frequency"],
enable_sata=description["enable_sata_drtio"], enable_sata=description["enable_sata_drtio"],
enable_sys5x=has_drtio_over_eem, enable_sys5x=has_drtio_over_eem,
with_wrpll=description["enable_wrpll"],
**kwargs) **kwargs)
if hw_rev == "v1.0": if hw_rev == "v1.0":
# EEM clock fan-out from Si5324, not MMCX # EEM clock fan-out from Si5324, not MMCX