occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

pipistrello: use mem_decoder

This commit is contained in:
Robert Jördens 2015-04-04 16:58:56 -06:00
parent e50661dac4
commit 0ae4492077
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
soc/targets/artiq_pipistrello.py
View File

@ -4,6 +4,7 @@ from migen.bank import wbgen
from mibuild.generic_platform import * from mibuild.generic_platform import *
from misoclib.com import gpio from misoclib.com import gpio
from misoclib.soc import mem_decoder
from targets.pipistrello import BaseSoC from targets.pipistrello import BaseSoC
from artiq.gateware import rtio, ad9858 from artiq.gateware import rtio, ad9858
@ -124,12 +125,12 @@ class ARTIQMidiSoC(BaseSoC):
rtio_csrs = self.rtio.get_csrs() rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs) self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus) self.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus)
self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs) self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
dds_pads = platform.request("dds") dds_pads = platform.request("dds")
self.submodules.dds = ad9858.AD9858(dds_pads) self.submodules.dds = ad9858.AD9858(dds_pads)
self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus) self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
self.comb += dds_pads.fud_n.eq(~fud) self.comb += dds_pads.fud_n.eq(~fud)