diff --git a/artiq/gateware/rtio/core.py b/artiq/gateware/rtio/core.py
index 69babebac..fa661e21c 100644
--- a/artiq/gateware/rtio/core.py
+++ b/artiq/gateware/rtio/core.py
@@ -167,6 +167,9 @@ class _OutputManager(Module):
                     (self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])
                     & ((self.ev.timestamp[:fine_ts_width] != buf.timestamp[:fine_ts_width])
                        |different_addresses))
+            else:
+                self.sync.rsys += collision.eq(
+                    (self.ev.timestamp == buf.timestamp) & different_addresses)
         else:
             self.sync.rsys += collision.eq(
                 self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])