From 05e2e1899a6e12e0c705a29306339dae5046aa82 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 9 Dec 2019 11:57:33 +0800 Subject: [PATCH] wrpll: update OBUFDS_GTE2 comment Seems O can fan out simultaneously to transceiver and fabric. Kasli is using ODIV2 for no particular reason. --- artiq/gateware/drtio/wrpll/ddmtd.py | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/artiq/gateware/drtio/wrpll/ddmtd.py b/artiq/gateware/drtio/wrpll/ddmtd.py index d5270de0d..6068b4dec 100644 --- a/artiq/gateware/drtio/wrpll/ddmtd.py +++ b/artiq/gateware/drtio/wrpll/ddmtd.py @@ -27,12 +27,9 @@ class DDMTDSamplerGTP(Module): self.rec_clk = Signal() self.main_xo = Signal() - # Getting the main XO signal from IBUFDS_GTE2 is problematic because: - # 1. the clock gets divided by 2 - # 2. the transceiver PLL craps out if an improper clock signal is applied, + # Getting the main XO signal from IBUFDS_GTE2 is problematic because + # the transceiver PLL craps out if an improper clock signal is applied, # so we are disabling the buffer until the clock is stable. - # 3. UG482 says "The O and ODIV2 outputs are not phase matched to each other", - # which may or may not be a problem depending on what it actually means. main_xo_se = Signal() self.specials += [ Instance("IBUFDS",