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sayma_amc: adopt MMCSPI bitbanging GPIO core 

* Requires changes to migen as in https://github.com/HarryMakes/migen/commits/sayma-mmcspi
This commit is contained in:
Harry Ho 2021-09-13 12:34:55 +08:00 committed by Sébastien Bourdeauducq
parent 9547a15162
commit 04ee775a9f
1 changed files with 16 additions and 0 deletions
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16
artiq/gateware/targets/sayma_amc.py
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@ -152,6 +152,22 @@ class SatelliteBase(MiniSoC):
self.crg.cd_sys.clk, self.crg.cd_sys.clk,
gth.txoutclk, gth.rxoutclk) gth.txoutclk, gth.rxoutclk)
# SSP1
# (Note: append() to csr_devices automatically adds "HAS_DEVICE_NAME_UPPERCASE"
# to Rust cfg, by misoc.integration.cpu_interface.get_rust_cfg().)
# MMC SPI GPIO input submodule
class Mmcspi(Module, AutoCSR):
def __init__(self, ssp):
self.submodules.cs_n = gpio.GPIOIn(ssp.cs_n)
self.submodules.clk = gpio.GPIOIn(ssp.clk)
self.submodules.mosi = gpio.GPIOIn(ssp.mosi)
# SPI GPIO core for bitbanging
ssp1 = self.platform.request("ssp1")
self.submodules.mmcspi = Mmcspi(ssp1)
self.csr_devices.append("mmcspi")
def add_rtio(self, rtio_channels): def add_rtio(self, rtio_channels):
# Only add MonInj core if there is anything to monitor # Only add MonInj core if there is anything to monitor
if any([len(c.probes) for c in rtio_channels]): if any([len(c.probes) for c in rtio_channels]):