From 03007b896e720804a32679bc15fcd13b0091bea7 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Mon, 7 Oct 2019 20:31:35 +0800
Subject: [PATCH] sayma_amc: sma -> mcx

---
 artiq/gateware/targets/sayma_amc.py | 36 ++++++++++++++---------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py
index be74a43f6..adc305e5e 100755
--- a/artiq/gateware/targets/sayma_amc.py
+++ b/artiq/gateware/targets/sayma_amc.py
@@ -246,14 +246,14 @@ class Satellite(SatelliteBase):
             phy = ttl_simple.Output(platform.request("user_led", i))
             self.submodules += phy
             rtio_channels.append(rtio.Channel.from_phy(phy))
-        sma_io = platform.request("sma_io", 0)
-        self.comb += sma_io.direction.eq(1)
-        phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
+        mcx_io = platform.request("mcx_io", 0)
+        self.comb += mcx_io.direction.eq(1)
+        phy = ttl_serdes_ultrascale.Output(4, mcx_io.level)
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy))
-        sma_io = platform.request("sma_io", 1)
-        self.comb += sma_io.direction.eq(0)
-        phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
+        mcx_io = platform.request("mcx_io", 1)
+        self.comb += mcx_io.direction.eq(0)
+        phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy))
 
@@ -298,14 +298,14 @@ class SimpleSatellite(SatelliteBase):
             phy = ttl_simple.Output(platform.request("user_led", i))
             self.submodules += phy
             rtio_channels.append(rtio.Channel.from_phy(phy))
-        sma_io = platform.request("sma_io", 0)
-        self.comb += sma_io.direction.eq(1)
-        phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
+        mcx_io = platform.request("mcx_io", 0)
+        self.comb += mcx_io.direction.eq(1)
+        phy = ttl_serdes_ultrascale.Output(4, mcx_io.level)
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy))
-        sma_io = platform.request("sma_io", 1)
-        self.comb += sma_io.direction.eq(0)
-        phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
+        mcx_io = platform.request("mcx_io", 1)
+        self.comb += mcx_io.direction.eq(0)
+        phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy))
 
@@ -416,14 +416,14 @@ class Master(MiniSoC, AMPSoC):
             phy = ttl_simple.Output(platform.request("user_led", i))
             self.submodules += phy
             rtio_channels.append(rtio.Channel.from_phy(phy))
-        sma_io = platform.request("sma_io", 0)
-        self.comb += sma_io.direction.eq(1)
-        phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
+        mcx_io = platform.request("mcx_io", 0)
+        self.comb += mcx_io.direction.eq(1)
+        phy = ttl_serdes_ultrascale.Output(4, mcx_io.level)
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy))
-        sma_io = platform.request("sma_io", 1)
-        self.comb += sma_io.direction.eq(0)
-        phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
+        mcx_io = platform.request("mcx_io", 1)
+        self.comb += mcx_io.direction.eq(0)
+        phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy))