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artiq_ddb_template: backport clk_div config fix 

add pll_en to json schema and ddb_template
set CLK IN divided by 1 as default when bypassing AD9910 PLL
raise ValueError when bypassing AD9912 PLL
This commit is contained in:
morgan 2024-02-16 16:05:48 +08:00 committed by Sébastien Bourdeauducq
parent 329c5c1af8
commit 02dfb3e5ac
2 changed files with 23 additions and 4 deletions
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12
artiq/coredevice/coredevice_generic.schema.json
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@ -302,6 +302,12 @@
"pll_n": { "pll_n": {
"type": "integer" "type": "integer"
}, },
"pll_en": {
"type": "integer",
"minimum": 0,
"maximum": 1,
"default": 1
},
"pll_vco": { "pll_vco": {
"type": "integer" "type": "integer"
}, },
@ -405,6 +411,12 @@
"type": "integer", "type": "integer",
"default": 32 "default": 32
}, },
"pll_en": {
"type": "integer",
"minimum": 0,
"maximum": 1,
"default": 1
},
"pll_vco": { "pll_vco": {
"type": "integer" "type": "integer"
} }

15
artiq/frontend/artiq_ddb_template.py
View File

@ -173,6 +173,11 @@ class PeripheralManager:
urukul_name = self.get_name("urukul") urukul_name = self.get_name("urukul")
synchronization = peripheral["synchronization"] synchronization = peripheral["synchronization"]
channel = count(0) channel = count(0)
pll_en = peripheral["pll_en"]
dds = peripheral["dds"]
if dds == "ad9912" and not pll_en:
raise ValueError("PLL bypass is not supported on AD9912")
self.gen(""" self.gen("""
device_db["eeprom_{name}"] = {{ device_db["eeprom_{name}"] = {{
"type": "local", "type": "local",
@ -231,14 +236,15 @@ class PeripheralManager:
"sync_device": {sync_device}, "sync_device": {sync_device},
"io_update_device": "ttl_{name}_io_update", "io_update_device": "ttl_{name}_io_update",
"refclk": {refclk}, "refclk": {refclk},
"clk_sel": {clk_sel} "clk_sel": {clk_sel},
"clk_div" : {clk_div}
}} }}
}}""", }}""",
name=urukul_name, name=urukul_name,
sync_device="\"ttl_{name}_sync\"".format(name=urukul_name) if synchronization else "None", sync_device="\"ttl_{name}_sync\"".format(name=urukul_name) if synchronization else "None",
refclk=peripheral.get("refclk", self.master_description["rtio_frequency"]), refclk=peripheral.get("refclk", self.master_description["rtio_frequency"]),
clk_sel=peripheral["clk_sel"]) clk_sel=peripheral["clk_sel"],
dds = peripheral["dds"] clk_div= 0 if pll_en else 1)
pll_vco = peripheral.get("pll_vco") pll_vco = peripheral.get("pll_vco")
for i in range(4): for i in range(4):
if dds == "ad9910": if dds == "ad9910":
@ -248,6 +254,7 @@ class PeripheralManager:
"module": "artiq.coredevice.ad9910", "module": "artiq.coredevice.ad9910",
"class": "AD9910", "class": "AD9910",
"arguments": {{ "arguments": {{
"pll_en": {pll_en},
"pll_n": {pll_n}, "pll_n": {pll_n},
"chip_select": {chip_select}, "chip_select": {chip_select},
"cpld_device": "{name}_cpld"{sw}{pll_vco}{sync_delay_seed}{io_update_delay} "cpld_device": "{name}_cpld"{sw}{pll_vco}{sync_delay_seed}{io_update_delay}
@ -258,7 +265,7 @@ class PeripheralManager:
uchn=i, uchn=i,
sw=",\n \"sw_device\": \"ttl_{name}_sw{uchn}\"".format(name=urukul_name, uchn=i) if len(peripheral["ports"]) > 1 else "", sw=",\n \"sw_device\": \"ttl_{name}_sw{uchn}\"".format(name=urukul_name, uchn=i) if len(peripheral["ports"]) > 1 else "",
pll_vco=",\n \"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "", pll_vco=",\n \"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "",
pll_n=peripheral.get("pll_n", 32), pll_n=peripheral.get("pll_n", 32), pll_en=pll_en,
sync_delay_seed=",\n \"sync_delay_seed\": \"eeprom_{}:{}\"".format(urukul_name, 64 + 4*i) if synchronization else "", sync_delay_seed=",\n \"sync_delay_seed\": \"eeprom_{}:{}\"".format(urukul_name, 64 + 4*i) if synchronization else "",
io_update_delay=",\n \"io_update_delay\": \"eeprom_{}:{}\"".format(urukul_name, 64 + 4*i) if synchronization else "") io_update_delay=",\n \"io_update_delay\": \"eeprom_{}:{}\"".format(urukul_name, 64 + 4*i) if synchronization else "")
elif dds == "ad9912": elif dds == "ad9912":