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base: occheung:a7faddabfaefe8a422c239df6184931379bbc1f6
Branches Tags
occheung:master
occheung:drtio-coremgmt
occheung:i2c-nack
occheung:fix-find-exidx
occheung:nac3ld-support
occheung:target2-rel
occheung:si5324-clkin
occheung:soc-sma-clkin
occheung:sma-clkin
occheung:release-6
M-Labs:master
M-Labs:release-8
M-Labs:release-7
M-Labs:release-6
...
compare: occheung:e68f778d53f850d3d0fb437c1e6b09b9095ef91c
Branches Tags
occheung:drtio-coremgmt
occheung:i2c-nack
occheung:fix-find-exidx
occheung:nac3ld-support
occheung:target2-rel
occheung:si5324-clkin
occheung:soc-sma-clkin
occheung:sma-clkin
occheung:master
occheung:release-6
M-Labs:master
M-Labs:release-8
M-Labs:release-7
M-Labs:release-6

2 Commits
a7faddabfa ... e68f778d53

Author SHA1 Message Date
occheung e68f778d53 kasli_soc: cleanup gateware 2022-03-07 17:30:58 +08:00
occheung a59c73e999 clock_cfg: simplify 2022-03-07 13:53:55 +08:00
2 changed files with 80 additions and 79 deletions
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2
src/gateware/kasli_soc.py
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@ -100,8 +100,6 @@ class SMAClkinForward(Module):
def __init__(self, platform): def __init__(self, platform):
sma_clkin = platform.request("sma_clkin") sma_clkin = platform.request("sma_clkin")
sma_clkin_se = Signal() sma_clkin_se = Signal()
sma_clkin_buffered = Signal()
sma_clkin_rebuf = Signal()
cdr_clk_se = Signal() cdr_clk_se = Signal()
cdr_clk = platform.request("cdr_clk") cdr_clk = platform.request("cdr_clk")
self.specials += [ self.specials += [

157
src/runtime/src/rtio_clocking.rs
View File

@ -121,101 +121,104 @@ fn init_drtio(timer: &mut GlobalTimer)
#[cfg(has_si5324)] #[cfg(has_si5324)]
fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) { fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
let si5324_settings = match clk { let (si5324_settings, si5324_ref_input) = match clk {
RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW
info!("using 10MHz reference to make 125MHz RTIO clock with PLL"); info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
si5324::FrequencySettings { (
n1_hs : 10, si5324::FrequencySettings {
nc1_ls : 4, n1_hs : 10,
n2_hs : 10, nc1_ls : 4,
n2_ls : 300, n2_hs : 10,
n31 : 6, n2_ls : 300,
n32 : 6, n31 : 6,
bwsel : 4, n32 : 6,
crystal_ref: false bwsel : 4,
} crystal_ref: false
},
si5324::Input::Ckin1
)
}, },
RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
info!("using 100MHz reference to make 125MHz RTIO clock with PLL"); info!("using 100MHz reference to make 125MHz RTIO clock with PLL");
si5324::FrequencySettings { (
n1_hs : 10, si5324::FrequencySettings {
nc1_ls : 4, n1_hs : 10,
n2_hs : 10, nc1_ls : 4,
n2_ls : 260, n2_hs : 10,
n31 : 52, n2_ls : 260,
n32 : 52, n31 : 52,
bwsel : 4, n32 : 52,
crystal_ref: false bwsel : 4,
} crystal_ref: false
},
si5324::Input::Ckin1
)
}, },
RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth
info!("using 125MHz reference to make 125MHz RTIO clock with PLL"); info!("using 125MHz reference to make 125MHz RTIO clock with PLL");
si5324::FrequencySettings { (
n1_hs : 5, si5324::FrequencySettings {
nc1_ls : 8, n1_hs : 5,
n2_hs : 7, nc1_ls : 8,
n2_ls : 360, n2_hs : 7,
n31 : 63, n2_ls : 360,
n32 : 63, n31 : 63,
bwsel : 4, n32 : 63,
crystal_ref: false bwsel : 4,
} crystal_ref: false
},
si5324::Input::Ckin1
)
}, },
RtioClock::Int_150 => { // 150MHz output, from crystal RtioClock::Int_150 => { // 150MHz output, from crystal
info!("using internal 150MHz RTIO clock"); info!("using internal 150MHz RTIO clock");
si5324::FrequencySettings { (
n1_hs : 9, si5324::FrequencySettings {
nc1_ls : 4, n1_hs : 9,
n2_hs : 10, nc1_ls : 4,
n2_ls : 33732, n2_hs : 10,
n31 : 7139, n2_ls : 33732,
n32 : 7139, n31 : 7139,
bwsel : 3, n32 : 7139,
crystal_ref: true bwsel : 3,
} crystal_ref: true
},
si5324::Input::Ckin2
)
}, },
RtioClock::Int_100 => { // 100MHz output, from crystal. RtioClock::Int_100 => { // 100MHz output, from crystal.
info!("using internal 100MHz RTIO clock"); info!("using internal 100MHz RTIO clock");
si5324::FrequencySettings { (
n1_hs : 9, si5324::FrequencySettings {
nc1_ls : 6, n1_hs : 9,
n2_hs : 10, nc1_ls : 6,
n2_ls : 33732, n2_hs : 10,
n31 : 7139, n2_ls : 33732,
n32 : 7139, n31 : 7139,
bwsel : 3, n32 : 7139,
crystal_ref: true bwsel : 3,
} crystal_ref: true
},
si5324::Input::Ckin2
)
}, },
RtioClock::Int_125 => { // 125MHz output, from crystal, 7 Hz RtioClock::Int_125 | _ => { // default: 125MHz output, from crystal, 7 Hz
info!("using internal 125MHz RTIO clock"); info!("using internal 125MHz RTIO clock");
si5324::FrequencySettings { (
n1_hs : 10, si5324::FrequencySettings {
nc1_ls : 4, n1_hs : 10,
n2_hs : 10, nc1_ls : 4,
n2_ls : 19972, n2_hs : 10,
n31 : 4565, n2_ls : 19972,
n32 : 4565, n31 : 4565,
bwsel : 4, n32 : 4565,
crystal_ref: true bwsel : 4,
} crystal_ref: true
} },
_ => { // same setting as Int_125, but fallback to default si5324::Input::Ckin2
warn!("rtio_clock setting '{:?}' is unsupported. Falling back to default internal 125MHz RTIO clock.", clk); )
si5324::FrequencySettings {
n1_hs : 10,
nc1_ls : 4,
n2_hs : 10,
n2_ls : 19972,
n31 : 4565,
n32 : 4565,
bwsel : 4,
crystal_ref: true
}
} }
}; };
let si5324_ref_input = si5324::Input::Ckin1;
// let si5324_ref_input = si5324::Input::Ckin2;
si5324::setup(i2c, &si5324_settings, si5324_ref_input, timer).expect("cannot initialize Si5324"); si5324::setup(i2c, &si5324_settings, si5324_ref_input, timer).expect("cannot initialize Si5324");
} }