forked from M-Labs/artiq-zynq
cargo fmt
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@ -691,7 +691,7 @@ impl Packet {
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length: length,
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length: length,
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data: data,
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data: data,
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}
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}
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},
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}
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0xdc => {
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0xdc => {
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let last = reader.read_bool()?;
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let last = reader.read_bool()?;
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let length = reader.read_u16()?;
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let length = reader.read_u16()?;
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@ -702,7 +702,7 @@ impl Packet {
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length: length,
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length: length,
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value: value,
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value: value,
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}
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}
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},
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}
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0xdd => Packet::CoreMgmtAck,
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0xdd => Packet::CoreMgmtAck,
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0xde => Packet::CoreMgmtNack,
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0xde => Packet::CoreMgmtNack,
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@ -1155,11 +1155,7 @@ impl Packet {
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writer.write_u16(length)?;
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writer.write_u16(length)?;
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writer.write_all(&data[0..length as usize])?;
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writer.write_all(&data[0..length as usize])?;
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}
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}
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Packet::CoreMgmtConfigReadReply {
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Packet::CoreMgmtConfigReadReply { last, length, value } => {
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last,
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length,
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value,
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} => {
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writer.write_u8(0xdc)?;
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writer.write_u8(0xdc)?;
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writer.write_bool(last)?;
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writer.write_bool(last)?;
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writer.write_u16(length)?;
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writer.write_u16(length)?;
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@ -139,7 +139,7 @@ async fn read_key(stream: &mut TcpStream) -> Result<String> {
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#[cfg(has_drtio)]
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#[cfg(has_drtio)]
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mod remote_coremgmt {
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mod remote_coremgmt {
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use io::{Cursor, ProtoWrite};
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use io::{Cursor, ProtoWrite};
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use libboard_artiq::drtioaux_proto::{MASTER_PAYLOAD_MAX_SIZE, Packet};
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use libboard_artiq::drtioaux_proto::{Packet, MASTER_PAYLOAD_MAX_SIZE};
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use super::*;
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use super::*;
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use crate::rtio_mgt::drtio;
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use crate::rtio_mgt::drtio;
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@ -351,11 +351,7 @@ mod remote_coremgmt {
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let mut buffer = Vec::<u8>::new();
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let mut buffer = Vec::<u8>::new();
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loop {
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loop {
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match reply {
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match reply {
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Packet::CoreMgmtConfigReadReply {
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Packet::CoreMgmtConfigReadReply { length, last, value } => {
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length,
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last,
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value,
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} => {
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buffer.extend(&value[..length as usize]);
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buffer.extend(&value[..length as usize]);
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if last {
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if last {
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@ -1132,10 +1132,7 @@ fn process_aux_packet(
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let key_slice = &key[..length as usize];
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let key_slice = &key[..length as usize];
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if !key_slice.is_ascii() {
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if !key_slice.is_ascii() {
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error!("invalid key");
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error!("invalid key");
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drtioaux::send(
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drtioaux::send(0, &drtioaux::Packet::CoreMgmtNack)
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0,
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&drtioaux::Packet::CoreMgmtNack,
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)
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} else {
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} else {
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let key = core::str::from_utf8(key_slice).unwrap();
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let key = core::str::from_utf8(key_slice).unwrap();
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if core_manager.fetch_config_value(key).is_ok() {
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if core_manager.fetch_config_value(key).is_ok() {
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@ -1149,10 +1146,7 @@ fn process_aux_packet(
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},
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},
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)
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)
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} else {
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} else {
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drtioaux::send(
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drtioaux::send(0, &drtioaux::Packet::CoreMgmtNack)
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0,
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&drtioaux::Packet::CoreMgmtNack,
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)
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}
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}
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}
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}
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}
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}
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@ -4,7 +4,7 @@ use core::cmp::min;
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#[cfg(has_drtio_routing)]
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#[cfg(has_drtio_routing)]
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use libboard_artiq::pl::csr;
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use libboard_artiq::pl::csr;
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use libboard_artiq::{drtio_routing, drtioaux,
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use libboard_artiq::{drtio_routing, drtioaux,
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drtioaux_proto::{PayloadStatus, SAT_PAYLOAD_MAX_SIZE, MASTER_PAYLOAD_MAX_SIZE}};
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drtioaux_proto::{PayloadStatus, MASTER_PAYLOAD_MAX_SIZE, SAT_PAYLOAD_MAX_SIZE}};
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pub struct SliceMeta {
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pub struct SliceMeta {
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pub destination: u8,
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pub destination: u8,
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