forked from M-Labs/artiq-zynq
drtio-mgmt: fix len order
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parent
f7e2089b5b
commit
be1f34bf7b
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@ -351,7 +351,7 @@ mod remote_coremgmt {
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let mut buffer = Vec::<u8>::new();
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loop {
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match reply {
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Packet::CoreMgmtConfigReadReply { length, last, value } => {
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Packet::CoreMgmtConfigReadReply { last, length, value } => {
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buffer.extend(&value[..length as usize]);
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if last {
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@ -403,8 +403,8 @@ mod remote_coremgmt {
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message.get_ref(),
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|slice, status, len: usize| Packet::CoreMgmtConfigWriteRequest {
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destination: destination,
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length: len as u16,
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last: status.is_last(),
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length: len as u16,
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data: *slice,
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},
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|reply| match reply {
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@ -1140,8 +1140,8 @@ fn process_aux_packet(
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drtioaux::send(
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0,
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&drtioaux::Packet::CoreMgmtConfigReadReply {
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length: meta.len as u16,
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last: meta.status.is_last(),
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length: meta.len as u16,
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value: value_slice,
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},
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)
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@ -1169,16 +1169,16 @@ fn process_aux_packet(
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drtioaux::send(
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0,
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&drtioaux::Packet::CoreMgmtConfigReadReply {
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length: meta.len as u16,
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last: meta.status.is_last(),
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length: meta.len as u16,
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value: value_slice,
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},
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)
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}
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drtioaux::Packet::CoreMgmtConfigWriteRequest {
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destination: _destination,
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length,
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last,
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length,
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data,
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} => {
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forward!(
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