From 9d3d73479abf97f9ae32f0847eb03009419fb952 Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Mon, 18 Jan 2021 14:35:17 +0800
Subject: [PATCH] spi: add delay margin

---
 src/spi.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/spi.rs b/src/spi.rs
index 7628a0a..c2f5dcc 100644
--- a/src/spi.rs
+++ b/src/spi.rs
@@ -133,7 +133,7 @@ impl <SPI: Transfer<u8>,
                 // Disable chip select
                 cortex_m::asm::delay(10_u32);
                 self.nss.set_high();
-                cortex_m::asm::delay(4_u32);
+                cortex_m::asm::delay(5_u32);
                 Ok(buf[2])
             },
             // TODO: Maybe too naive?
@@ -141,7 +141,7 @@ impl <SPI: Transfer<u8>,
                 // Disable chip select
                 cortex_m::asm::delay(10_u32);
                 self.nss.set_high();
-                cortex_m::asm::delay(4_u32);
+                cortex_m::asm::delay(5_u32);
                 Err(SpiPortError::TransferError)
             }
         }