diff --git a/src/lib.rs b/src/lib.rs
index d96cbaf..baf065f 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -67,6 +67,7 @@ impl <SPI: Transfer<u8>,
 impl <SPI: Transfer<u8>,
       NSS: OutputPin,
       Delay: DelayUs<u16>> EthController for SpiEth<SPI, NSS, Delay> {
+    fn init_dev(&mut self) -> Result<(), EthControllerError> {
         // Write 0x1234 to EUDAST
         self.spi_port.write_reg_16b(spi::addrs::EUDAST, 0x1234)?;
         // Verify that EUDAST is 0x1234
@@ -83,14 +84,14 @@ impl <SPI: Transfer<u8>,
         let econ2 = self.spi_port.read_reg_8b(spi::addrs::ECON2)?;
         self.spi_port.write_reg_8b(spi::addrs::ECON2, 0x10 | (econ2 & 0b11101111))?;
         // Wait for 25us
-        delay.delay_us(25_u16);
+        self.spi_port.delay_us(25_u16);
         // Verify that EUDAST is 0x0000
         eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?;
         if eudast != 0x0000 {
             return Err(EthControllerError::GeneralError)
         }
         // Wait for 256us
-        delay.delay_us(256_u16);
+        self.spi_port.delay_us(256_u16);
         Ok(())
     }