forked from M-Labs/zynq-rs
62 lines
1.6 KiB
Rust
62 lines
1.6 KiB
Rust
use volatile_register::{RO, WO, RW};
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use crate::{register, register_bit, register_bits, regs::*};
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#[repr(C)]
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pub struct RegisterBlock {
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pub control: Control,
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pub mode: Mode,
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pub intrpt_en: RW<u32>,
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pub intrpt_dis: RW<u32>,
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pub intrpt_mask: RO<u32>,
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pub chnl_int_sts: WO<u32>,
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pub baud_rate_gen: BaudRateGen,
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pub rcvr_timeout: RW<u32>,
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pub rcvr_fifo_trigger_level: RW<u32>,
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pub modem_ctrl: RW<u32>,
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pub modem_sts: RW<u32>,
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pub channel_sts: ChannelSts,
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pub tx_rx_fifo: TxRxFifo,
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pub baud_rate_divider: BaudRateDiv,
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pub flow_delay: RW<u32>,
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pub unused0: RO<u32>,
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pub unused1: RO<u32>,
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pub tx_fifo_trigger_level: RW<u32>,
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}
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register!(control, Control, RW, u32);
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register_bit!(control, rxrst, 0);
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register_bit!(control, txrst, 1);
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register_bit!(control, rxen, 2);
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register_bit!(control, rxdis, 3);
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register_bit!(control, txen, 4);
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register_bit!(control, txdis, 5);
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register!(mode, Mode, RW, u32);
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register_bits!(mode, par, u8, 3, 5);
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register!(baud_rate_gen, BaudRateGen, RW, u32);
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register_bits!(baud_rate_gen, cd, u16, 0, 15);
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register!(channel_sts, ChannelSts, RO, u32);
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register_bit!(channel_sts, txfull, 4);
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register!(tx_rx_fifo, TxRxFifo, RW, u32);
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register_bits!(tx_rx_fifo, data, u32, 0, 31);
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register!(baud_rate_div, BaudRateDiv, RW, u32);
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register_bits!(baud_rate_div, bdiv, u8, 0, 7);
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impl RegisterBlock {
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const UART0: *mut Self = 0xE0000000 as *mut _;
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const UART1: *mut Self = 0xE0001000 as *mut _;
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pub fn uart0() -> &'static mut Self {
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unsafe { &mut *Self::UART0 }
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}
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pub fn uart1() -> &'static mut Self {
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unsafe { &mut *Self::UART1 }
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}
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}
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