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zynq-rs
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135 Commits 4 Branches 0 Tags 1.5 MiB
Commit Graph

50 Commits

Author SHA1 Message Date
Astro 7cdf6c0918 start implementation of a StaticAllocator 2019-10-28 00:43:57 +01:00
Astro fc39885d3b zynq::ddr: fix clock setup 2019-10-28 00:43:09 +01:00
Astro 85bd506132 zynq::ddr: parameters 2019-10-27 20:38:06 +01:00
Astro 9b4f07f37c zynq::ddr, main: parameters, memtest 2019-10-25 23:19:34 +02:00
Astro 4cf5283ba8 zynq::ddr: implement reset_ddrc(), add to main 2019-10-24 01:39:14 +02:00
Astro c046bbf8a2 move slcr, clocks, uart, eth into src/zynq/ 2019-10-21 22:19:03 +02:00
Astro b541160f38 add zynq::axi_hp 2019-10-18 23:46:00 +02:00
Björn Stein 1804c4c6e8 cortex_a9: add proper L1 cache invalidation 2019-10-18 00:11:51 +02:00
Astro 4e9c38527e rm debug, delint 2019-09-29 03:01:24 +02:00
Astro 0f6bc68d1f eth: prepare link change detection 2019-09-29 02:30:03 +02:00
Astro 378755a0ce main: bump RX_LEN/TX_LEN to 2 2019-09-29 01:40:38 +02:00
Astro 4c62ce0dad main: restrict eth buffers to 1 each 2019-08-19 02:21:36 +02:00
Astro 45ed5f6c5b abort handlers: replace panic with infinite loop 2019-08-19 01:18:12 +02:00
Astro d11e581862 main: setup smoltcp 
still panics, leading to a DataAbort
 2019-08-19 01:18:12 +02:00
Astro b8818863c4 read clocks 2019-08-17 03:20:04 +02:00
Astro 1f9ad5ff62 delint 2019-08-11 00:56:54 +02:00
Astro d001593a36 rm bcmp 2019-08-06 22:03:23 +02:00
Astro 2db35d063f define bcmp 
other solution might be defining a non-linux target
 2019-08-06 14:15:44 +02:00
Astro 5823d90db1 phy: implement control, status, reset 2019-06-25 21:48:47 +02:00
Astro ce74fe7299 eth: prepare tx 2019-06-22 01:39:44 +02:00
Astro 6757ceb76c eth rx: error handling 2019-06-22 01:20:18 +02:00
Astro e5881a14ad eth rx: descriptors/buffers as refs 
avoid moving these after their addresses have been written to the qbar
 2019-06-21 00:58:18 +02:00
Astro d65398205f add a println! for convenience 2019-06-20 00:30:18 +02:00
Astro b3b65f9b74 eth: find Phy 2019-06-19 00:21:17 +02:00
Astro 1634513bc7 mmu: align l1_table 2019-06-18 19:18:47 +02:00
Astro 9bebfb49bc begin MMU implementation 2019-06-17 03:32:10 +02:00
Astro 69b65b5f72 cortex_a9 regs: allow defining bit fields 2019-06-17 01:36:11 +02:00
Astro 1e16beb707 cortex_a9::regs: use crate::regs interface 2019-06-12 00:20:23 +02:00
Astro 81a892b618 eth: recv_next() 2019-06-10 02:44:29 +02:00
Astro f07a541c99 eth: model rx/tx state with type parameters 2019-06-09 20:10:41 +02:00
Astro 824e91e6cb eth: rx/tx desc list, start_rx 2019-06-09 01:02:10 +02:00
Astro 2d7fed6c59 link again compiler_builtins 
required for memset etc
 2019-06-09 01:00:58 +02:00
Astro d447f1cc45 main: probe for PHYs 2019-06-04 23:50:11 +02:00
Astro acf995d7da soft_reset: rm unreachable! 2019-05-31 00:19:20 +02:00
Astro bf4f5108f4 main: add UART_RATE 2019-05-31 00:19:01 +02:00
Astro 2df74cc055 add static exception handling 2019-05-30 20:30:19 +02:00
Astro 5b15bb5c0a main: make boot_core0() naked 2019-05-30 02:41:44 +02:00
Astro a645d13f4b add uart panic handler 2019-05-28 00:28:35 +02:00
Astro 75bb755327 extend linker script 2019-05-27 22:38:10 +02:00
Astro d10ffe9eb9 eth: setup mio_pins, configure net_cfg 2019-05-25 03:06:39 +02:00
Astro 51c39f032e run with the cora z7-10 2019-05-25 02:38:48 +02:00
Astro 1033648c3e add l1_cache_init() 2019-05-23 19:05:06 +02:00
Astro fd7fd0db14 main: rm unused feature #![feature(global_asm)] 2019-05-23 16:06:41 +02:00
Astro ea62d4fdec uart: make baudrate configurable, run at 115,200 baud 2019-05-23 15:50:53 +02:00
Astro 47ec0116a9 use uart1 with more configuration 2019-05-21 01:30:54 +02:00
Astro c88374eab1 fix SP init 2019-05-20 01:21:22 +02:00
Astro b754581452 eth: add regs and init 2019-05-07 19:28:33 +02:00
Astro 275f297309 uart: impl fmt::Write 2019-05-07 16:45:31 +02:00
Astro 55957eea09 regs macros 2019-05-06 23:56:53 +02:00
Astro 9b414e2408 PoC: boot, uart output in qemu 2019-05-05 14:56:23 +02:00