From a6955edf14486c9a45664f89113015e52d4f6601 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 9 Sep 2020 20:10:05 +0800 Subject: [PATCH] add Red Pitaya support (WIP) --- experiments/Cargo.toml | 1 + experiments/src/main.rs | 7 ++++++ libboard_zynq/Cargo.toml | 1 + libboard_zynq/src/clocks/source.rs | 2 ++ libboard_zynq/src/ddr/mod.rs | 33 +++++++++++++++++++++++++- libboard_zynq/src/sdio/mod.rs | 12 ++++++++++ libboard_zynq/src/stdio.rs | 2 +- libboard_zynq/src/uart/mod.rs | 2 +- libcortex_a9/Cargo.toml | 1 + libsupport_zynq/Cargo.toml | 1 + openocd/digilent-hs2.cfg | 12 ++++++++++ openocd/redpitaya.cfg | 38 ++++++++++++++++++++++++++++++ 12 files changed, 109 insertions(+), 3 deletions(-) create mode 100644 openocd/digilent-hs2.cfg create mode 100644 openocd/redpitaya.cfg diff --git a/experiments/Cargo.toml b/experiments/Cargo.toml index ee79096..ee4b5b0 100644 --- a/experiments/Cargo.toml +++ b/experiments/Cargo.toml @@ -8,6 +8,7 @@ edition = "2018" [features] target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"] target_cora_z7_10 = ["libboard_zynq/target_cora_z7_10", "libsupport_zynq/target_cora_z7_10"] +target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya"] default = ["target_zc706"] [dependencies] diff --git a/experiments/src/main.rs b/experiments/src/main.rs index fcf208f..8b97830 100644 --- a/experiments/src/main.rs +++ b/experiments/src/main.rs @@ -109,6 +109,8 @@ pub fn main_core0() { const CPU_FREQ: u32 = 800_000_000; #[cfg(feature = "target_cora_z7_10")] const CPU_FREQ: u32 = 650_000_000; + #[cfg(feature = "target_redpitaya")] + const CPU_FREQ: u32 = 800_000_000; info!("Setup clock sources..."); ArmPll::setup(2 * CPU_FREQ); @@ -123,6 +125,11 @@ pub fn main_core0() { IoPll::setup(1_000_000_000); libboard_zynq::stdio::drop_uart(); } + #[cfg(feature = "target_redpitaya")] + { + IoPll::setup(1_000_000_000); + libboard_zynq::stdio::drop_uart(); + } info!("PLLs set up"); let clocks = zynq::clocks::Clocks::get(); info!( diff --git a/libboard_zynq/Cargo.toml b/libboard_zynq/Cargo.toml index 718c79c..45b259a 100644 --- a/libboard_zynq/Cargo.toml +++ b/libboard_zynq/Cargo.toml @@ -8,6 +8,7 @@ edition = "2018" [features] target_zc706 = [] target_cora_z7_10 = [] +target_redpitaya = [] ipv6 = [ "smoltcp/proto-ipv6" ] [dependencies] diff --git a/libboard_zynq/src/clocks/source.rs b/libboard_zynq/src/clocks/source.rs index 18348c5..ca590a3 100644 --- a/libboard_zynq/src/clocks/source.rs +++ b/libboard_zynq/src/clocks/source.rs @@ -6,6 +6,8 @@ use super::slcr; pub const PS_CLK: u32 = 33_333_333; #[cfg(feature = "target_cora_z7_10")] pub const PS_CLK: u32 = 50_000_000; +#[cfg(feature = "target_redpitaya")] +pub const PS_CLK: u32 = 33_333_333; /// (pll_fdiv_max, (pll_cp, pll_res, lock_cnt)) const PLL_FDIV_LOCK_PARAM: &[(u16, (u8, u8, u16))] = &[ diff --git a/libboard_zynq/src/ddr/mod.rs b/libboard_zynq/src/ddr/mod.rs index 05fb8c7..7d8019e 100644 --- a/libboard_zynq/src/ddr/mod.rs +++ b/libboard_zynq/src/ddr/mod.rs @@ -14,6 +14,10 @@ const DDR_FREQ: u32 = 666_666_666; /// Micron MT41K256M16HA-125: 800 MHz DDR3L, max supported 533 MHz const DDR_FREQ: u32 = 525_000_000; +#[cfg(feature = "target_redpitaya")] +/// Alliance Memory AS4C256M16D3B: 800 MHz DDR3 +const DDR_FREQ: u32 = 800_000_000; + /// MT41K256M16HA-125 const DCI_FREQ: u32 = 10_000_000; @@ -147,6 +151,15 @@ impl DdrRam { .dci_type(slcr::DdriobDciType::Termination) .output_en(slcr::DdriobOutputEn::Obuf); #[cfg(feature = "target_cora_z7_10")] + let data1_config = slcr::DdriobConfig::zeroed() + .pullup_en(true); + #[cfg(feature = "target_redpitaya")] + let data0_config = slcr::DdriobConfig::zeroed() + .inp_type(slcr::DdriobInputType::VrefDifferential) + .term_en(true) + .dci_type(slcr::DdriobDciType::Termination) + .output_en(slcr::DdriobOutputEn::Obuf); + #[cfg(feature = "target_redpitaya")] let data1_config = slcr::DdriobConfig::zeroed() .pullup_en(true); slcr.ddriob_data0.write(data0_config); @@ -169,7 +182,15 @@ impl DdrRam { #[cfg(feature = "target_cora_z7_10")] let diff1_config = slcr::DdriobConfig::zeroed() .pullup_en(true); - + #[cfg(feature = "target_redpitaya")] + let diff0_config = slcr::DdriobConfig::zeroed() + .inp_type(slcr::DdriobInputType::Differential) + .term_en(true) + .dci_type(slcr::DdriobDciType::Termination) + .output_en(slcr::DdriobOutputEn::Obuf); + #[cfg(feature = "target_redpitaya")] + let diff1_config = slcr::DdriobConfig::zeroed() + .pullup_en(true); slcr.ddriob_diff0.write(diff0_config); slcr.ddriob_diff1.write(diff1_config); @@ -200,6 +221,12 @@ impl DdrRam { .vref_ext_en_lower(false) .vref_ext_en_upper(false) ); + #[cfg(feature = "target_redpitaya")] + slcr.ddriob_ddr_ctrl.modify(|_, w| w + .vref_int_en(false) + .vref_ext_en_lower(true) + .vref_ext_en_upper(false) + ); }); } @@ -293,6 +320,8 @@ impl DdrRam { let width = regs::DataBusWidth::Width32bit; #[cfg(feature = "target_cora_z7_10")] let width = regs::DataBusWidth::Width16bit; + #[cfg(feature = "target_redpitaya")] + let width = regs::DataBusWidth::Width16bit; self.regs.ddrc_ctrl.modify(|_, w| w .soft_rstb(false) .powerdown_en(false) @@ -322,6 +351,8 @@ impl DdrRam { let megabytes = 1023; #[cfg(feature = "target_cora_z7_10")] let megabytes = 511; + #[cfg(feature = "target_redpitaya")] + let megabytes = 511; megabytes * 1024 * 1024 } diff --git a/libboard_zynq/src/sdio/mod.rs b/libboard_zynq/src/sdio/mod.rs index b96f447..1fc4415 100644 --- a/libboard_zynq/src/sdio/mod.rs +++ b/libboard_zynq/src/sdio/mod.rs @@ -116,6 +116,18 @@ impl Sdio { .speed(true), ); } + // redpitaya card detect pin + #[cfg(feature = "target_redpitaya")] + { + unsafe { + slcr.sd0_wp_cd_sel.write(46 << 16); + } + slcr.mio_pin_46.write( + slcr::MioPin46::zeroed() + .io_type(slcr::IoBufferType::Lvcmos25) + .speed(true), + ); + } slcr.sdio_rst_ctrl.reset_sdio0(); slcr.aper_clk_ctrl.enable_sdio0(); slcr.sdio_clk_ctrl.enable_sdio0(); diff --git a/libboard_zynq/src/stdio.rs b/libboard_zynq/src/stdio.rs index 6005b76..39ba61f 100644 --- a/libboard_zynq/src/stdio.rs +++ b/libboard_zynq/src/stdio.rs @@ -45,7 +45,7 @@ impl DerefMut for LazyUart { fn deref_mut(&mut self) -> &mut Uart { match self { LazyUart::Uninitialized => { - #[cfg(feature = "target_cora_z7_10")] + #[cfg(any(feature = "target_cora_z7_10", feature = "target_redpitaya"))] let uart = Uart::uart0(UART_RATE); #[cfg(feature = "target_zc706")] let uart = Uart::uart1(UART_RATE); diff --git a/libboard_zynq/src/uart/mod.rs b/libboard_zynq/src/uart/mod.rs index a94c4b4..6a63471 100644 --- a/libboard_zynq/src/uart/mod.rs +++ b/libboard_zynq/src/uart/mod.rs @@ -13,7 +13,7 @@ pub struct Uart { } impl Uart { - #[cfg(feature = "target_cora_z7_10")] + #[cfg(any(feature = "target_cora_z7_10", feature = "target_redpitaya"))] pub fn uart0(baudrate: u32) -> Self { slcr::RegisterBlock::unlocked(|slcr| { // Route UART 0 RxD/TxD Signals to MIO Pins diff --git a/libcortex_a9/Cargo.toml b/libcortex_a9/Cargo.toml index 3c62f74..11f03d3 100644 --- a/libcortex_a9/Cargo.toml +++ b/libcortex_a9/Cargo.toml @@ -7,6 +7,7 @@ edition = "2018" [features] target_zc706 = [] target_cora_z7_10 = [] +target_redpitaya = [] power_saving = [] default = ["target_zc706"] diff --git a/libsupport_zynq/Cargo.toml b/libsupport_zynq/Cargo.toml index 7339fe8..950a716 100644 --- a/libsupport_zynq/Cargo.toml +++ b/libsupport_zynq/Cargo.toml @@ -8,6 +8,7 @@ edition = "2018" [features] target_zc706 = ["libboard_zynq/target_zc706"] target_cora_z7_10 = ["libboard_zynq/target_cora_z7_10"] +target_redpitaya = ["libboard_zynq/target_redpitaya"] panic_handler = [] dummy_irq_handler = [] alloc_core = [] diff --git a/openocd/digilent-hs2.cfg b/openocd/digilent-hs2.cfg new file mode 100644 index 0000000..5c42e02 --- /dev/null +++ b/openocd/digilent-hs2.cfg @@ -0,0 +1,12 @@ +# this is the original file from OpenOCD, but with ftdi_device_desc +# removed because some cables don't have it programmed. + +# this supports JTAG-HS2 (and apparently Nexys4 as well) + +interface ftdi +ftdi_vid_pid 0x0403 0x6014 + +ftdi_channel 0 +ftdi_layout_init 0x00e8 0x60eb + +reset_config none diff --git a/openocd/redpitaya.cfg b/openocd/redpitaya.cfg new file mode 100644 index 0000000..becaa37 --- /dev/null +++ b/openocd/redpitaya.cfg @@ -0,0 +1,38 @@ +source ./digilent-hs2.cfg +adapter_khz 1000 + +set PL_TAPID 0x13722093 +set SMP 1 + +source ./zynq-7000.cfg + +reset_config none + +set XC7_JSHUTDOWN 0x0d +set XC7_JPROGRAM 0x0b +set XC7_JSTART 0x0c +set XC7_BYPASS 0x3f + +proc xc7_program {tap} { + global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS + irscan $tap $XC7_JSHUTDOWN + irscan $tap $XC7_JPROGRAM + runtest 60000 + #JSTART prevents this from working... + #irscan $tap $XC7_JSTART + runtest 2000 + irscan $tap $XC7_BYPASS + runtest 2000 +} + +pld device virtex2 zynq.tap 1 +init +xc7_program zynq.tap + +halt + +# Disable MMU +targets $_TARGETNAME_1 +arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd] +targets $_TARGETNAME_0 +arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd]