Create EMIO PLLSource

libboard_zynq/src/clocks/mod.rs

@@ -1,3 +1,5 @@
+use core::unimplemented;
+
 use libregister::{RegisterR, RegisterRW};
 use super::slcr;
 pub use slcr::ArmPllSource;
@@ -101,6 +103,8 @@ impl Clocks {
                 self.ddr,
             slcr::PllSource::IoPll =>
                 self.io,
+            slcr::PllSource::EMIO =>
+                unimplemented!(),
         };
         pll / u32::from(uart_clk_ctrl.divisor())
     }
@@ -115,6 +119,8 @@ impl Clocks {
                 self.ddr,
             slcr::PllSource::IoPll =>
                 self.io,
+            slcr::PllSource::EMIO =>
+                unimplemented!(),
         };
         pll / u32::from(sdio_clk_ctrl.divisor())
     }

libboard_zynq/src/eth/mod.rs

@@ -16,6 +16,8 @@ pub mod tx;
 use super::time::Milliseconds;
 use embedded_hal::timer::CountDown;
 
+use libcortex_a9::asm;
+
 /// Size of all the buffers
 pub const MTU: usize = 1536;
 /// Maximum MDC clock
@@ -65,17 +67,31 @@ impl Gem for Gem0 {
             slcr.gem0_clk_ctrl.write(
                 // 0x0050_0801: 8, 5: 100 Mb/s
                 // ...: 8, 1: 1000 Mb/s
+                #[cfg(not(feature = "target_ebaz4205"))]
                 slcr::GemClkCtrl::zeroed()
                     .clkact(true)
                     .srcsel(slcr::PllSource::IoPll)
                     .divisor(divisor0 as u8)
+                    .divisor1(divisor1 as u8),
+                // ebaz4205 -- EMIO
+                #[cfg(feature = "target_ebaz4205")]
+                slcr::GemClkCtrl::zeroed()
+                    .clkact(true)
+                    .srcsel(slcr::PllSource::EMIO)
+                    .divisor(divisor0 as u8)
                     .divisor1(divisor1 as u8)
             );
             // Enable gem0 recv clock
             slcr.gem0_rclk_ctrl.write(
                 // 0x0000_0801
+                #[cfg(not(feature = "target_ebaz4205"))]
+                slcr::RclkCtrl::zeroed()
+                    .clkact(true),
+                // ebaz4205 -- EMIO
+                #[cfg(feature = "target_ebaz4205")]
                 slcr::RclkCtrl::zeroed()
                     .clkact(true)
+                    .srcsel(true)
             );
         });
     }
@@ -154,6 +170,7 @@ pub struct Eth<GEM: Gem, RX, TX> {
 
 impl Eth<Gem0, (), ()> {
     pub fn eth0(macaddr: [u8; 6]) -> Self {
+        #[cfg(not(feature = "target_ebaz4205"))]
         slcr::RegisterBlock::unlocked(|slcr| {
             // Manual example: 0x0000_1280
             // MDIO
@@ -281,6 +298,16 @@ impl Eth<Gem0, (), ()> {
             );
         });
 
+        // This didn't help, might not need, keep for now, and remove later to test.
+        #[cfg(feature = "target_ebaz4205")]
+        slcr::RegisterBlock::unlocked(|slcr| {
+            // VREF internal generator
+            slcr.gpiob_ctrl.write(
+                slcr::GpiobCtrl::zeroed()
+                    .vref_en(true)
+            );
+        });
+
         Self::gem0(macaddr)
     }
 
@@ -301,8 +328,12 @@ impl Eth<Gem1, (), ()> {
 
 impl<GEM: Gem> Eth<GEM, (), ()> {
     fn gem_common(macaddr: [u8; 6]) -> Self {
+        #[cfg(not(feature = "target_ebaz4205"))]
         GEM::setup_clock(TX_1000);
 
+        #[cfg(feature = "target_ebaz4205")]
+        GEM::setup_clock(TX_100);
+
         #[cfg(feature="target_kasli_soc")]
         {
             let mut eth_reset_pin = PhyRst::rst_pin();
@@ -317,6 +348,14 @@ impl<GEM: Gem> Eth<GEM, (), ()> {
 
         inner.configure(macaddr);
 
+
+        // Used for debugging MDIO
+        // loop {
+        //     let _phy = Phy::find(&mut inner);
+        //     for _ in 0..100_000_000 {
+        //         asm::nop();
+        //     }
+        // }
         let phy = Phy::find(&mut inner).expect("phy");
         phy.reset(&mut inner);
         phy.restart_autoneg(&mut inner);

libboard_zynq/src/eth/phy/mod.rs

@@ -83,7 +83,8 @@ pub struct Phy {
 const OUI_MARVELL: u32 = 0x005043;
 const OUI_REALTEK: u32 = 0x000732;
 const OUI_LANTIQ : u32 = 0x355969;
-const OUI_ICPLUS : u32 = 0x02430c;
+const OUI_ICPLUS : u32 = 0x0090c3;
+// const OUI_ICPLUS : u32 = 0x02430c;
 
 //only change pages on Kasli-SoC's Marvel 88E11xx
 #[cfg(feature="target_kasli_soc")]
@@ -123,7 +124,6 @@ impl Phy {
                     // IP101G-DS-R01
                     model: 5,
                     rev: 4,
-                    ..
                 }) => true,
                 _ => false,
             }

libboard_zynq/src/slcr.rs

@@ -9,9 +9,11 @@ use libregister::{
 
 #[repr(u8)]
 pub enum PllSource {
-    IoPll  = 0b00,
+    IoPll  = 0b000,
-    ArmPll = 0b10,
+    ArmPll = 0b010,
-    DdrPll = 0b11,
+    DdrPll = 0b011,
+    // Ethernet controller via EMIO
+    EMIO   = 0b100,
 }
 
 #[repr(u8)]

libconfig/src/net_settings.rs

@@ -55,14 +55,14 @@ pub fn get_addresses(cfg: &Config) -> NetAddresses {
     let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x55]);
     #[cfg(feature = "target_redpitaya")]
     let mut ipv4_addr = IpAddress::v4(192, 168, 1, 55);
-    #[cfg(feature = "target_ebaz4205")]
-    let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x56]);
-    #[cfg(feature = "target_ebaz4205")]
-    let mut ipv4_addr = IpAddress::v4(192, 168, 1, 56);
     #[cfg(feature = "target_kasli_soc")]
     let mut hardware_addr = get_address_from_eeprom();
     #[cfg(feature = "target_kasli_soc")]
     let mut ipv4_addr = IpAddress::v4(192, 168, 1, 56);
+    #[cfg(feature = "target_ebaz4205")]
+    let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x57]);
+    #[cfg(feature = "target_ebaz4205")]
+    let mut ipv4_addr = IpAddress::v4(192, 168, 1, 57);
 
     if let Ok(Ok(addr)) = cfg.read_str("mac").map(|s| s.parse()) {
         hardware_addr = addr;