From 3841accd9c833913385efeb40f1abaed8b56a940 Mon Sep 17 00:00:00 2001
From: Astro <astro@spaceboyz.net>
Date: Sat, 9 May 2020 02:53:58 +0200
Subject: [PATCH] libboard_zynq: fix ddr memtest range

---
 libboard_zynq/src/ddr/mod.rs | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/libboard_zynq/src/ddr/mod.rs b/libboard_zynq/src/ddr/mod.rs
index 924513a..d4166c4 100644
--- a/libboard_zynq/src/ddr/mod.rs
+++ b/libboard_zynq/src/ddr/mod.rs
@@ -221,7 +221,7 @@ impl DdrRam {
     /// overlaps with OCM.
     pub fn size(&self) -> usize {
         #[cfg(feature = "target_zc706")]
-        let megabytes = 1022;
+        let megabytes = 1023;
         #[cfg(feature = "target_cora_z7_10")]
         let megabytes = 511;
 
@@ -237,9 +237,9 @@ impl DdrRam {
         for (i, pattern) in patterns.iter().enumerate() {
             info!("memtest phase {} (status: {:?})", i, self.status());
 
-            for megabyte in 0..=(slice.len() / (1024 * 1024)) {
+            for megabyte in 0..slice.len() / (1024 * 1024) {
                 let start = megabyte * 1024 * 1024 / 4;
-                let end = ((megabyte + 1) * 1024 * 1024 / 4).min(slice.len());
+                let end = ((megabyte + 1) * 1024 * 1024 / 4);
                 for b in slice[start..end].iter_mut() {
                     expected.map(|expected| {
                         let read: u32 = *b;