2020-01-03 18:07:07 +08:00
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source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
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2020-01-15 05:07:19 +08:00
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source [find xilinx-tcl.cfg]
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2019-10-31 07:28:19 +08:00
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adapter_khz 1000
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2019-06-29 08:41:36 +08:00
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2019-09-29 05:53:40 +08:00
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set PL_TAPID 0x23731093
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2019-06-29 08:41:36 +08:00
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set SMP 1
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source ./zynq-7000.cfg
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source ./xilinx-tcl.cfg
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source ./ps7_init.tcl
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2020-01-03 18:07:07 +08:00
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reset_config srst_only srst_open_drain
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adapter_nsrst_assert_width 250
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adapter_nsrst_delay 400
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2019-06-29 08:41:36 +08:00
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set XC7_JSHUTDOWN 0x0d
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set XC7_JPROGRAM 0x0b
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set XC7_JSTART 0x0c
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set XC7_BYPASS 0x3f
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proc xc7_program {tap} {
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global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
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irscan $tap $XC7_JSHUTDOWN
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irscan $tap $XC7_JPROGRAM
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runtest 60000
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#JSTART prevents this from working...
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#irscan $tap $XC7_JSTART
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runtest 2000
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irscan $tap $XC7_BYPASS
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runtest 2000
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}
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pld device virtex2 zynq.tap 1
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init
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xc7_program zynq.tap
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xilinx_ps7_init
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# Disable MMU
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targets $_TARGETNAME_1
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arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd]
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targets $_TARGETNAME_0
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arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd]
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2020-01-15 05:07:19 +08:00
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# uncomment the below to load up a bitstream onto the fpga
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#pld load 0 blinker_migen.bit
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#exit
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