forked from M-Labs/nix-scripts
41 lines
1.3 KiB
Diff
41 lines
1.3 KiB
Diff
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diff --git a/mirny.py b/mirny.py
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index 6c041de..73991b1 100644
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--- a/mirny.py
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+++ b/mirny.py
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@@ -135,7 +135,7 @@ class SR(Module):
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)
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]
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- def connect_ext(self, ext, adr, mask):
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+ def connect_ext(self, ext, adr, mask, sdi_passthrough=False):
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adr &= mask
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self._check_intersection(adr, mask)
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self._slaves.append((ext, adr, mask))
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@@ -146,12 +146,16 @@ class SR(Module):
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stb.ce.eq(self.bus.re),
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# don't glitch with &stb.o
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ext.sck.eq(self.ext.sck),
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- ext.sdi.eq(self.ext.sdi & stb.o),
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ext.cs.eq(stb.o),
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If(stb.o,
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self.ext.sdo.eq(ext.sdo),
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),
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]
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+ # Almazny shares one SDI with 4 devices, it cannot be masked by stb
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+ if sdi_passthrough:
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+ self.comb += ext.sdi.eq(self.ext.sdi)
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+ else:
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+ self.comb += ext.sdi.eq(self.ext.sdi & stb.o),
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def intersection(a, b):
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@@ -360,7 +364,7 @@ class Mirny(Module):
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]
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ext = Record(ext_layout)
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- self.sr.connect_ext(ext, adr=i + 12, mask=mask)
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+ self.sr.connect_ext(ext, adr=i + 12, mask=mask, sdi_passthrough=True)
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self.comb += [
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mezz[i + 3].oe.eq(1),
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mezz[i + 3].o.eq(~ext.cs), # Almazny REG_LATCH
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