morgan 7827c7b803 Gateware: kasli_soc WRPLL setup ... kasli_soc: use enable_wrpll from json to switch from si5324 to si549 kasli_soc: add wrpll for all variants kasli_soc: add gtx & main tag nFIQ for all variants kasli_soc: add clk_synth_se for master & satellite kasli_soc: add wrpll_refclk for runtime kasli_soc: add skewtester for satman kasli_soc: add WRPLL_REF_CLK config for firmware		2024-04-11 15:18:10 +08:00
..
acpki.py	acpki: working	2020-09-09 21:24:49 +08:00
analyzer.py	analyzer: report AXI bus errors	2020-07-20 19:51:22 +08:00
config.py	refactor `write_rustc_cfg_file()`	2023-09-11 11:48:19 +08:00
ddmtd.py	Gateware: WRPLL	2024-04-11 15:18:04 +08:00
dma.py	dma: report AXI bus error	2020-07-21 12:47:20 +08:00
drtio_aux_controller.py	gateware: add DRTIO	2021-10-08 16:12:30 +08:00
endianness.py	dma: fix endianness issues	2020-07-16 17:27:08 +08:00
kasli_soc.py	Gateware: kasli_soc WRPLL setup	2024-04-11 15:18:10 +08:00
si549.py	Gateware: WRPLL	2024-04-11 15:18:04 +08:00
test_dma.py	RTIO/SYS Clock merge	2023-02-17 15:52:43 +08:00
wrpll.py	Gateware: WRPLL	2024-04-11 15:18:04 +08:00
zc706.py	kasli_soc & zc706: Fix GTX Clock Path during INIT	2023-11-07 18:55:08 +08:00
zynq_clocking.py	zynq_clocking: Allow ext signal to set cur_clk csr	2023-11-07 18:55:08 +08:00