sven-oxionics 656cbf4546 kasli_soc: use sed_lanes value from HW description ... https://github.com/m-labs/artiq/pull/1745 added a field for setting the number of SED lanes to the HW description. This commit makes it so that the setting is used for Kasli Soc as well.		2023-10-06 15:37:56 +01:00
..
acpki.py	acpki: working	2020-09-09 21:24:49 +08:00
analyzer.py	analyzer: report AXI bus errors	2020-07-20 19:51:22 +08:00
config.py	refactor write_rustc_cfg_file()	2023-09-11 11:48:19 +08:00
dma.py	dma: report AXI bus error	2020-07-21 12:47:20 +08:00
drtio_aux_controller.py	gateware: add DRTIO	2021-10-08 16:12:30 +08:00
endianness.py	dma: fix endianness issues	2020-07-16 17:27:08 +08:00
kasli_soc.py	kasli_soc: use sed_lanes value from HW description	2023-10-06 15:37:56 +01:00
test_dma.py	RTIO/SYS Clock merge	2023-02-17 15:52:43 +08:00
zc706.py	consolidate all write..file() into config.py	2023-09-11 11:48:19 +08:00
zynq_clocking.py	RTIO/SYS Clock merge	2023-02-17 15:52:43 +08:00