gateware: Add default TTLs to EBAZ4205 (#335)

Co-authored-by: newell <newell.jensen@gmail.com>
Co-committed-by: newell <newell.jensen@gmail.com>

examples/ebaz4205/device_db.py

@@ -53,13 +53,21 @@ device_db = {
     },
 }
 
+# TTLs starting at RTIO channel 2, ending at RTIO channel 15
+for i in range(2, 16):
+    device_db["ttl" + str(i)] = {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLInOut",
+        "arguments": {"channel": i},
+    }
 
 device_db.update(
     spi0={
         "type": "local",
         "module": "artiq.coredevice.spi2",
         "class": "SPIMaster",
-        "arguments": {"channel": 2},
+        "arguments": {"channel": 16},
     },
     dds0={
         "type": "local",

flake.lock

@@ -11,11 +11,11 @@
         "src-pythonparser": "src-pythonparser"
       },
       "locked": {
-        "lastModified": 1727765117,
-        "narHash": "sha256-P4PgnsXNL4kXjSAhRpXzkq17j8bEaJAqNLSH2Vt+DY0=",
+        "lastModified": 1731636768,
+        "narHash": "sha256-Oqa7G8E9lFIFouYE2uP5ii4Bo6eKHmUUHwj4uievMdE=",
         "ref": "refs/heads/master",
-        "rev": "333623e24bdec00783bc89c1e8b6b49a74bc9e1c",
-        "revCount": 9020,
+        "rev": "9aae89be69fa3ab1dd0a75f399ffc6cf208818d2",
+        "revCount": 9048,
         "type": "git",
         "url": "https://github.com/m-labs/artiq.git"
       },
@@ -102,11 +102,11 @@
     },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1727348695,
-        "narHash": "sha256-J+PeFKSDV+pHL7ukkfpVzCOO7mBSrrpJ3svwBFABbhI=",
+        "lastModified": 1731319897,
+        "narHash": "sha256-PbABj4tnbWFMfBp6OcUK5iGy1QY+/Z96ZcLpooIbuEI=",
         "owner": "NixOS",
         "repo": "nixpkgs",
-        "rev": "1925c603f17fc89f4c8f6bf6f631a802ad85d784",
+        "rev": "dc460ec76cbff0e66e269457d7b728432263166c",
         "type": "github"
       },
       "original": {
@@ -153,11 +153,11 @@
         ]
       },
       "locked": {
-        "lastModified": 1724921939,
-        "narHash": "sha256-/S5iip1LHLiCP2VY7PwClDteP9ZMRZvzzKR1LZuV3fs=",
+        "lastModified": 1728371104,
+        "narHash": "sha256-PPnAyDedUQ7Og/Cby9x5OT9wMkNGTP8GS53V6N/dk4w=",
         "owner": "m-labs",
         "repo": "sipyco",
-        "rev": "32ddd78ff3641b75054793ea0d5681c951766754",
+        "rev": "094a6cd63ffa980ef63698920170e50dc9ba77fd",
         "type": "github"
       },
       "original": {
@@ -185,11 +185,11 @@
     "src-misoc": {
       "flake": false,
       "locked": {
-        "lastModified": 1715647536,
-        "narHash": "sha256-q+USDcaKHABwW56Jzq8u94iGPWlyLXMyVt0j/Gyg+IE=",
+        "lastModified": 1729234629,
+        "narHash": "sha256-TLsTCXV5AC2xh+bS7EhBVBKqdqIU3eKrnlWcFF9LtAM=",
         "ref": "refs/heads/master",
-        "rev": "fea9de558c730bc394a5936094ae95bb9d6fa726",
-        "revCount": 2455,
+        "rev": "6085a312bca26adeca6584e37d08c8ba2e1d6e38",
+        "revCount": 2460,
         "submodules": true,
         "type": "git",
         "url": "https://github.com/m-labs/misoc.git"
@@ -240,11 +240,11 @@
         ]
       },
       "locked": {
-        "lastModified": 1728110308,
-        "narHash": "sha256-MAoFbcDgr+ZjptFCWfthK+tTnR1NcfuO6tvYhNM2Pwo=",
+        "lastModified": 1731704957,
+        "narHash": "sha256-wxYzmzXZZIPslnLk0rEEC5qqYoyHl3m7MG39IMA4Zak=",
         "ref": "refs/heads/master",
-        "rev": "cc20478d91e30e1448a4304df7003caed2981b71",
-        "revCount": 651,
+        "rev": "5815baf88b613757ae252850c342c9c44ed1243d",
+        "revCount": 652,
         "type": "git",
         "url": "https://git.m-labs.hk/m-labs/zynq-rs"
       },

src/gateware/ebaz4205.py

@@ -5,7 +5,7 @@ import argparse
 import analyzer
 import dma
 from artiq.gateware import rtio
-from artiq.gateware.rtio.phy import dds, spi2, ttl_simple
+from artiq.gateware.rtio.phy import spi2, ttl_simple
 from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
 from config import write_csr_file, write_mem_file, write_rustc_cfg_file
 from migen import *
@@ -91,6 +91,17 @@ _spi = [
 ]
 
 
+# Connector DATA1
+def _create_ttl():
+    _ttl = []
+
+    for idx, elem in enumerate([x for x in range(5, 21) if x not in (10, 12)]):
+        _ttl.append(
+            ("ttl", idx, Pins("DATA1:DATA1-{}".format(elem)), IOStandard("LVCMOS33")),
+        )
+    return _ttl
+
+
 class EBAZ4205(SoCCore):
     def __init__(self, rtio_clk=125e6, acpki=False):
         self.acpki = acpki
@@ -105,6 +116,7 @@ class EBAZ4205(SoCCore):
         platform.add_extension(_ddr)
         platform.add_extension(_i2c)
         platform.add_extension(_spi)
+        platform.add_extension(_create_ttl())
 
         gmii = platform.request("gmii")
         platform.add_period_constraint(gmii.rx_clk, 10)
@@ -180,6 +192,13 @@ class EBAZ4205(SoCCore):
             self.submodules += phy
             self.rtio_channels.append(rtio.Channel.from_phy(phy))
 
+        for i in range(14):
+            print("TTL at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
+            ttl = self.platform.request("ttl", i)
+            phy = ttl_simple.InOut(ttl)
+            self.submodules += phy
+            self.rtio_channels.append(rtio.Channel.from_phy(phy))
+
         print("SPI at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
         spi_phy = spi2.SPIMaster(platform.request("spi"))
         self.submodules += spi_phy