Commit Graph

59 Commits

Author SHA1 Message Date
1931957bc0 Updated cargoSha256 2020-09-02 10:15:52 +08:00
6ede148810 Updated build scripts 2020-09-01 15:57:20 +08:00
653d143784 updated cargoSha256 2020-09-01 15:49:46 +08:00
49689dedf1 update cargosha256 2020-08-25 16:25:27 +08:00
ba162b3997 Fix pure build 2020-08-25 14:51:39 +08:00
2faf74f708 Revert "drop FSBL"
Gitea issue #94

This reverts commit 67ff3c36e2.
2020-08-25 10:49:00 +08:00
bb35d6b46a default.nix: update cargosha256 2020-08-17 19:21:25 +02:00
3a8a025d5f update dependencies, zc706 -> zynq-rs 2020-08-06 20:33:23 +08:00
e7752a3d6d runtime/kernel: fixes core0 memory leak.
Fixes #85
2020-08-06 09:39:49 +08:00
a9c40f7478 Updated cargoSha256. 2020-08-04 14:40:02 +08:00
a5938b0fd6 default.nix: add ACPKI-enabled builds 2020-08-04 13:17:33 +08:00
7f4ccc9ded Updated cargoSha256 2020-08-04 10:47:52 +08:00
673ad3fd8e update cargosha256 2020-07-25 12:22:31 +08:00
845f98242b update cargosha256 2020-07-23 01:06:50 +02:00
e0560a2db9 expose libm functions to kernel 2020-07-21 13:50:33 +08:00
367d54293b update cargosha256 2020-07-19 16:47:49 +08:00
92405ffe91 logger: changed from RefCell to Mutex. 2020-07-15 17:04:16 +08:00
62f39e2c08 mgmt: Implemented network log access. 2020-07-13 15:15:06 +08:00
f1f7fe8da6 fix gateware pure build 2020-07-13 10:44:25 +08:00
e3ff21b1b5 create gateware folder 2020-07-11 17:49:54 +08:00
67ff3c36e2 drop FSBL
All SZL and Zynq startup issues seem resolved.
2020-07-07 19:44:14 +08:00
a8de572014 set up PL clocks 2020-07-07 19:40:32 +08:00
e6cf3e90d3 update zc706 2020-07-07 12:50:05 +08:00
de2c2af523 use new exception vectors 2020-07-06 21:16:32 +08:00
bbc1ffec8e szl: disable ps7_init 2020-07-06 12:31:13 +08:00
bbe6812792 add network address config code 2020-07-06 12:04:22 +08:00
2df1a647df update cargosha256 2020-07-06 01:12:23 +08:00
3bd4643009 use fpu_enable from zc706 2020-07-06 00:18:28 +08:00
6f37128911 use clang-unwrapped 2020-07-02 21:50:19 +08:00
e6028ec091 update cargosha256 2020-07-02 21:41:35 +08:00
8807854b2b fix cargoSha256 2020-07-02 10:31:14 +08:00
d8745074b4 update dependencies 2020-06-27 02:29:45 +02:00
a71ee143ac update dependencies 2020-06-25 20:21:44 +08:00
f750234cb5 update dependencies 2020-06-18 18:33:32 +02:00
854a50a0ba fsbl: clean up buildInputs 2020-06-17 16:23:41 +08:00
ec9a70ecc3 FSBL: changed to self-built FSBL (#13)
Co-authored-by: pca006132 <john.lck40@gmail.com>
2020-06-17 16:19:59 +08:00
e43511c95f update dependencies 2020-06-16 18:08:12 +08:00
0dc0bb391d
add support for loading bitstream from bootimage. 2020-06-16 17:45:54 +08:00
f9ccf908dd update dependencies 2020-06-15 17:14:03 +08:00
dec245e637 default.nix: also use BIF format to contain bitstream for SZL 2020-06-15 17:03:27 +08:00
dc78868109 update dependencies and add fatfs 2020-06-11 17:36:23 +08:00
de2618045a update cargoSha256 2020-06-07 22:00:23 +08:00
7216e9c4be update cargoSha256 2020-06-05 19:26:50 +08:00
15b2b253cf build for NIST variants 2020-05-14 15:30:50 +08:00
af08b1ad00 update dependencies 2020-05-14 09:28:16 +08:00
aeefdc862d update dependencies 2020-05-09 13:48:27 +08:00
4464b85ab3 move build artifacts out of tree 2020-05-07 13:52:40 +08:00
90faeb6fa2 use new core1 startup mechanism 2020-05-06 22:16:34 +08:00
ae2cee5f7e also work around mkbootimage potential bug with szl 2020-05-06 17:47:27 +08:00
27466036a7 work around boot.bin/fsbl problems
* Use fsbl.elf sent to me by Xilinx tech support. None of the other FSBL images for ZC706, including the official one from 2019.2-zc706-release.tar.xz, appear to work (no UART output, no FPGA DONE).
* Prevent boot.bin creation tool from crashing due to long paths.
2020-05-06 17:38:01 +08:00