From d59c283129221c5025ebc2e3dd5a3b452b91fae1 Mon Sep 17 00:00:00 2001
From: newell <newell.jensen@gmail.com>
Date: Mon, 30 Sep 2024 14:27:54 -0700
Subject: [PATCH] Update gateware

---
 src/gateware/ebaz4205.py | 38 +++++++++++++++++---------------------
 1 file changed, 17 insertions(+), 21 deletions(-)

diff --git a/src/gateware/ebaz4205.py b/src/gateware/ebaz4205.py
index 25b7a2d..744abf3 100644
--- a/src/gateware/ebaz4205.py
+++ b/src/gateware/ebaz4205.py
@@ -10,10 +10,7 @@ from migen_axi.integration.soc_core import SoCCore
 from misoc.interconnect.csr import *
 
 from artiq.gateware import rtio
-from artiq.gateware.rtio.phy import (
-    ttl_simple,
-    dds,  # Need to create module for AD9834
-)
+from artiq.gateware.rtio.phy import ttl_simple
 from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
 
 import dma
@@ -78,11 +75,10 @@ _ddr = [
 
 
 class EBAZ4205(SoCCore):
-    def __init__(self, acpki=False):
+    def __init__(self, rtio_clk=100e6, acpki=False):
         self.acpki = acpki
 
         platform = ebaz4205.Platform()
-        # platform = Platform()
         platform.toolchain.bitstream_commands.extend(
             [
                 "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
@@ -91,12 +87,13 @@ class EBAZ4205(SoCCore):
         platform.add_extension(_ps)
         platform.add_extension(_ddr)
 
-        # FCLK is tied to pin U18
-        platform.add_extension(
-            [
-                ("fclk", 0, Pins("U18"), IOStandard("LVCMOS33")),
-            ]
-        )
+        ## Uncomment if your EBAZ4205 doesn't have a PHY XTAL
+        ## Clock for PHY is tied to pin U18
+        # platform.add_extension(
+        #     [
+        #         ("phy_clk", 0, Pins("U18"), IOStandard("LVCMOS33")),
+        #     ]
+        # )
 
         gmii = platform.request("gmii")
 
@@ -116,22 +113,19 @@ class EBAZ4205(SoCCore):
             ident=ident,
         )
         fix_serdes_timing_path(platform)
-        # When using pd_cd_sys, the default clock coming from fclk.clk[0] is 100 MHz
-        self.config["RTIO_FREQUENCY"] = "100"
+        self.config["RTIO_FREQUENCY"] = str(rtio_clk / 1e6)
         platform.add_period_constraint(self.ps7.cd_sys.clk, 10)
 
         self.comb += [
             self.ps7.enet0.enet.gmii.tx_clk.eq(gmii.tx_clk),
             self.ps7.enet0.enet.gmii.rx_clk.eq(gmii.rx_clk),
         ]
-
         self.clock_domains.cd_eth_rx = ClockDomain(reset_less=False)
         self.clock_domains.cd_eth_tx = ClockDomain(reset_less=False)
         self.comb += [
             ClockSignal("eth_rx").eq(gmii.rx_clk),
             ClockSignal("eth_tx").eq(gmii.tx_clk),
         ]
-
         self.sync.eth_tx += [
             gmii.txd.eq(self.ps7.enet0.enet.gmii.txd),
             gmii.tx_en.eq(self.ps7.enet0.enet.gmii.tx_en),
@@ -141,11 +135,12 @@ class EBAZ4205(SoCCore):
             self.ps7.enet0.enet.gmii.rx_dv.eq(gmii.rx_dv),
         ]
 
-        # FCLK
-        fclk = platform.request("fclk")
-        self.comb += fclk.eq(self.ps7.fclk.clk[0])
+        ## Uncomment if your EBAZ4205 doesn't have a PHY XTAL
+        ## Left for the user to do, setup a 25 MHz clock for phy_clk.
+        # phy_clk = platform.request("phy_clk")
+        # ...
 
-        # MDIO/MDC
+        # MDIO
         mdio = platform.request("mdio")
         self.comb += [
             mdio.mdc.eq(self.ps7.enet0.enet.mdio.mdc),
@@ -230,12 +225,13 @@ def main():
     parser.add_argument(
         "-g", default=None, help="build gateware into the specified directory"
     )
+    parser.add_argument("--rtio_clk", default=100e6, help="RTIO Clock Frequency (Hz)")
     parser.add_argument(
         "--acpki", default=False, action="store_true", help="enable ACPKI"
     )
     args = parser.parse_args()
 
-    soc = EBAZ4205()
+    soc = EBAZ4205(rtio_clk=int(args.rtio_clk), acpki=args.acpki)
     soc.finalize()
 
     if args.r is not None: