forked from M-Labs/artiq-zynq
change write_rustc_cfg_file to follow artiq repo
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parent
3d43bc8b15
commit
d019021ff5
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@ -113,7 +113,6 @@ class SMAClkinForward(Module):
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class GenericStandalone(SoCCore):
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def __init__(self, description, acpki=False):
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self.acpki = acpki
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self.rustc_cfg = dict()
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platform = kasli_soc.Platform()
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platform.toolchain.bitstream_commands.extend([
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@ -129,8 +128,8 @@ class GenericStandalone(SoCCore):
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self.submodules += SMAClkinForward(self.platform)
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self.rustc_cfg["has_si5324"] = None
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self.rustc_cfg["si5324_soft_reset"] = None
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.submodules.rtio_crg = RTIOCRG(self.platform)
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@ -160,14 +159,14 @@ class GenericStandalone(SoCCore):
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self.csr_devices.append("rtio_core")
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if self.acpki:
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self.rustc_cfg["ki_impl"] = "acp"
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self.config["KI_IMPL"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.rustc_cfg["ki_impl"] = "csr"
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self.config["KI_IMPL"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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@ -187,7 +186,7 @@ class GenericStandalone(SoCCore):
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self.csr_devices.append("rtio_analyzer")
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if has_grabber:
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self.rustc_cfg["has_grabber"] = None
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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for grabber in self.grabber_csr_group:
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self.platform.add_false_path_constraints(
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@ -200,7 +199,6 @@ class GenericMaster(SoCCore):
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rtio_clk_freq = description["rtio_frequency"]
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self.acpki = acpki
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self.rustc_cfg = dict()
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platform = kasli_soc.Platform()
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platform.toolchain.bitstream_commands.extend([
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@ -229,8 +227,8 @@ class GenericMaster(SoCCore):
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(platform)
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self.rustc_cfg["has_si5324"] = None
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self.rustc_cfg["si5324_soft_reset"] = None
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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@ -275,8 +273,8 @@ class GenericMaster(SoCCore):
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memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), size)
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self.axi2csr.register_port(coreaux.get_rx_port(), size)
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self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
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self.rustc_cfg["has_drtio"] = None
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self.rustc_cfg["has_drtio_routing"] = None
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.add_csr_group("drtio", drtio_csr_group)
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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@ -285,14 +283,14 @@ class GenericMaster(SoCCore):
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self.csr_devices.append("rtio_core")
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if self.acpki:
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self.rustc_cfg["ki_impl"] = "acp"
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self.config["KI_IMPL"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.rustc_cfg["ki_impl"] = "csr"
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self.config["KI_IMPL"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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@ -316,7 +314,7 @@ class GenericMaster(SoCCore):
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self.csr_devices.append("rtio_analyzer")
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if has_grabber:
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self.rustc_cfg["has_grabber"] = None
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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@ -326,7 +324,6 @@ class GenericSatellite(SoCCore):
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rtio_clk_freq = description["rtio_frequency"]
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self.acpki = acpki
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self.rustc_cfg = dict()
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platform = kasli_soc.Platform()
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platform.toolchain.bitstream_commands.extend([
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@ -343,7 +340,6 @@ class GenericSatellite(SoCCore):
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
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self.csr_devices.append("rtio_crg")
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self.rustc_cfg["has_rtio_crg"] = None
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fix_serdes_timing_path(platform)
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data_pads = [platform.request("sfp", i) for i in range(4)]
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@ -412,21 +408,21 @@ class GenericSatellite(SoCCore):
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# and registered in PS interface
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# manually, because software refers to rx/tx by halves of entire memory block, not names
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self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
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self.rustc_cfg["has_drtio"] = None
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self.rustc_cfg["has_drtio_routing"] = None
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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self.add_csr_group("drtiorep", drtiorep_csr_group)
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if self.acpki:
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self.rustc_cfg["ki_impl"] = "acp"
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self.config["KI_IMPL"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.rustc_cfg["ki_impl"] = "csr"
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self.config["KI_IMPL"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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@ -449,7 +445,7 @@ class GenericSatellite(SoCCore):
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self.csr_devices.append("rtio_moninj")
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rtio_clk_period = 1e9/rtio_clk_freq
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self.rustc_cfg["rtio_frequency"] = str(rtio_clk_freq/1e6)
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("cdr_clk"),
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@ -459,9 +455,8 @@ class GenericSatellite(SoCCore):
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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self.rustc_cfg["has_si5324"] = None
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self.rustc_cfg["has_siphaser"] = None
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self.rustc_cfg["si5324_soft_reset"] = None
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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gtx0 = self.drtio_transceiver.gtxs[0]
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platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
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@ -475,7 +470,7 @@ class GenericSatellite(SoCCore):
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self.crg.cd_sys.clk, gtx.rxoutclk)
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if has_grabber:
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self.rustc_cfg["has_grabber"] = None
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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# no RTIO CRG here
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@ -494,11 +489,14 @@ def write_csr_file(soc, filename):
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def write_rustc_cfg_file(soc, filename):
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with open(filename, "w") as f:
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for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)):
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if v is None:
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f.write("{}\n".format(k))
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for name, origin, busword, obj in soc.get_csr_regions():
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f.write("has_{}\n".format(name.lower()))
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for name, value in soc.get_constants():
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if name.upper().startswith("CONFIG_"):
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if value is None:
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f.write("{}\n".format(name.lower()[7:]))
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else:
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f.write("{}=\"{}\"\n".format(k, v))
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f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value)))
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def main():
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