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Add variant to gateware

This commit is contained in:
newell 2024-10-07 20:32:07 -07:00
parent f8fd081e02
commit 968ee60d55
2 changed files with 37 additions and 16 deletions

View File

@ -114,12 +114,11 @@
"nist_clock_satellite" "nist_qc2_satellite" "acpki_nist_clock_satellite" "acpki_nist_qc2_satellite"
"nist_clock_satellite_100mhz" "nist_qc2_satellite_100mhz" "acpki_nist_clock_satellite_100mhz" "acpki_nist_qc2_satellite_100mhz"
];
board-package-set = { target, variant ? null, json ? null }: let
board-package-set = { target, variant, json ? null }: let
szl = zynqpkgs."${target}-szl";
fsbl = zynqpkgs."${target}-fsbl";
fwtype = if builtins.elem variant sat_variants then "satman" else "runtime";
targetVariantStr = if variant == null then "${target}" else "${target}-${variant}";
firmware = rustPlatform.buildRustPackage rec {
name = "firmware";
src = ./src;
@ -143,7 +142,7 @@
export CLANG_EXTRA_INCLUDE_DIR="${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include"
export CARGO_HOME=$(mktemp -d cargo-home.XXX)
export ZYNQ_RS=${zynq-rs}
make TARGET=${target} GWARGS="${if json == null then if target == "ebaz4205" then "" else "-V ${if variant == null then "" else variant}" else json};" ${fwtype}
make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}" ${fwtype}
'';
installPhase = ''
@ -158,7 +157,7 @@
dontFixup = true;
auditable = false;
};
gateware = pkgs.runCommand "${targetVariantStr}-gateware"
gateware = pkgs.runCommand "${target}-${variant}-gateware"
{
nativeBuildInputs = [
(pkgs.python3.withPackages(ps: [ ps.jsonschema artiqpkgs.migen migen-axi artiqpkgs.misoc artiqpkgs.artiq ]))
@ -166,21 +165,21 @@
];
}
''
python ${./src/gateware}/${target}.py -g build ${if json == null then if target == "ebaz4205" then "" else "-V ${if variant == null then "" else variant}" else json}
python ${./src/gateware}/${target}.py -g build ${if json == null then "-V ${variant}" else json}
mkdir -p $out $out/nix-support
cp build/top.bit $out
echo file binary-dist $out/top.bit >> $out/nix-support/hydra-build-products
'';
# SZL startup
jtag = pkgs.runCommand "${targetVariantStr}-jtag" {}
jtag = pkgs.runCommand "${target}-${variant}-jtag" {}
''
mkdir $out
ln -s ${szl}/szl.elf $out
ln -s ${firmware}/${fwtype}.bin $out
ln -s ${gateware}/top.bit $out
'';
sd = pkgs.runCommand "${targetVariantStr}-sd"
sd = pkgs.runCommand "${target}-${variant}-sd"
{
buildInputs = [ zynqpkgs.mkbootimage ];
}
@ -206,7 +205,7 @@
'';
# FSBL startup
fsbl-sd = pkgs.runCommand "${targetVariantStr}-fsbl-sd"
fsbl-sd = pkgs.runCommand "${target}-${variant}-fsbl-sd"
{
buildInputs = [ zynqpkgs.mkbootimage ];
}
@ -229,14 +228,14 @@
echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
'';
in {
"${targetVariantStr}-firmware" = firmware;
"${targetVariantStr}-gateware" = gateware;
"${targetVariantStr}-jtag" = jtag;
"${targetVariantStr}-sd" = sd;
"${target}-${variant}-firmware" = firmware;
"${target}-${variant}-gateware" = gateware;
"${target}-${variant}-jtag" = jtag;
"${target}-${variant}-sd" = sd;
} // (
if builtins.elem target fsblTargets
then {
"${targetVariantStr}-fsbl-sd" = fsbl-sd;
"${target}-${variant}-fsbl-sd" = fsbl-sd;
}
else {}
);
@ -366,7 +365,7 @@
(board-package-set { target = "kasli_soc"; variant = "demo"; json = ./demo.json; }) //
(board-package-set { target = "kasli_soc"; variant = "master"; json = ./kasli-soc-master.json; }) //
(board-package-set { target = "kasli_soc"; variant = "satellite"; json = ./kasli-soc-satellite.json; }) //
(board-package-set { target = "ebaz4205"; });
(board-package-set { target = "ebaz4205"; variant = "base"; });
hydraJobs = packages.x86_64-linux // { inherit zc706-hitl-tests; inherit gateware-sim; inherit fmt-check; };

View File

@ -212,6 +212,14 @@ class EBAZ4205(SoCCore):
self.csr_devices.append("rtio_analyzer")
class BASE(EBAZ4205):
def __init__(self, rtio_clk, acpki):
EBAZ4205.__init__(self, rtio_clk, acpki)
VARIANTS = {cls.__name__.lower(): cls for cls in [BASE]}
def main():
parser = argparse.ArgumentParser(
description="ARTIQ port to the EBAZ4205 control card of Ebit E9+ BTC miner"
@ -232,11 +240,25 @@ def main():
)
parser.add_argument("--rtio-clk", default=125e6, help="RTIO Clock Frequency (Hz)")
parser.add_argument(
"--acpki", default=False, action="store_true", help="enable ACPKI"
"-V",
"--variant",
default="base",
help="variant: " "[acpki_]base" "(default: %(default)s)",
)
args = parser.parse_args()
soc = EBAZ4205(rtio_clk=int(args.rtio_clk), acpki=args.acpki)
rtio_clk = int(args.rtio_clk)
variant = args.variant.lower()
acpki = variant.startswith("acpki_")
if acpki:
variant = variant[6:]
try:
cls = VARIANTS[variant]
except KeyError:
raise SystemExit("Invalid variant (-V/--variant)")
soc = cls(rtio_clk=rtio_clk, acpki=acpki)
soc.finalize()
if args.r is not None: