forked from M-Labs/artiq-zynq
Add variant to gateware
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parent
f8fd081e02
commit
968ee60d55
27
flake.nix
27
flake.nix
@ -114,12 +114,11 @@
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"nist_clock_satellite" "nist_qc2_satellite" "acpki_nist_clock_satellite" "acpki_nist_qc2_satellite"
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"nist_clock_satellite_100mhz" "nist_qc2_satellite_100mhz" "acpki_nist_clock_satellite_100mhz" "acpki_nist_qc2_satellite_100mhz"
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];
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board-package-set = { target, variant ? null, json ? null }: let
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board-package-set = { target, variant, json ? null }: let
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szl = zynqpkgs."${target}-szl";
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fsbl = zynqpkgs."${target}-fsbl";
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fwtype = if builtins.elem variant sat_variants then "satman" else "runtime";
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targetVariantStr = if variant == null then "${target}" else "${target}-${variant}";
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firmware = rustPlatform.buildRustPackage rec {
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name = "firmware";
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src = ./src;
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@ -143,7 +142,7 @@
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export CLANG_EXTRA_INCLUDE_DIR="${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include"
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export CARGO_HOME=$(mktemp -d cargo-home.XXX)
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export ZYNQ_RS=${zynq-rs}
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make TARGET=${target} GWARGS="${if json == null then if target == "ebaz4205" then "" else "-V ${if variant == null then "" else variant}" else json};" ${fwtype}
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make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}" ${fwtype}
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'';
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installPhase = ''
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@ -158,7 +157,7 @@
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dontFixup = true;
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auditable = false;
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};
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gateware = pkgs.runCommand "${targetVariantStr}-gateware"
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gateware = pkgs.runCommand "${target}-${variant}-gateware"
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{
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nativeBuildInputs = [
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(pkgs.python3.withPackages(ps: [ ps.jsonschema artiqpkgs.migen migen-axi artiqpkgs.misoc artiqpkgs.artiq ]))
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@ -166,21 +165,21 @@
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];
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}
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''
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python ${./src/gateware}/${target}.py -g build ${if json == null then if target == "ebaz4205" then "" else "-V ${if variant == null then "" else variant}" else json}
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python ${./src/gateware}/${target}.py -g build ${if json == null then "-V ${variant}" else json}
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mkdir -p $out $out/nix-support
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cp build/top.bit $out
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echo file binary-dist $out/top.bit >> $out/nix-support/hydra-build-products
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'';
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# SZL startup
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jtag = pkgs.runCommand "${targetVariantStr}-jtag" {}
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jtag = pkgs.runCommand "${target}-${variant}-jtag" {}
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''
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mkdir $out
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ln -s ${szl}/szl.elf $out
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ln -s ${firmware}/${fwtype}.bin $out
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ln -s ${gateware}/top.bit $out
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'';
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sd = pkgs.runCommand "${targetVariantStr}-sd"
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sd = pkgs.runCommand "${target}-${variant}-sd"
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{
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buildInputs = [ zynqpkgs.mkbootimage ];
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}
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@ -206,7 +205,7 @@
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'';
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# FSBL startup
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fsbl-sd = pkgs.runCommand "${targetVariantStr}-fsbl-sd"
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fsbl-sd = pkgs.runCommand "${target}-${variant}-fsbl-sd"
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{
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buildInputs = [ zynqpkgs.mkbootimage ];
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}
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@ -229,14 +228,14 @@
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echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
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'';
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in {
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"${targetVariantStr}-firmware" = firmware;
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"${targetVariantStr}-gateware" = gateware;
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"${targetVariantStr}-jtag" = jtag;
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"${targetVariantStr}-sd" = sd;
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"${target}-${variant}-firmware" = firmware;
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"${target}-${variant}-gateware" = gateware;
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"${target}-${variant}-jtag" = jtag;
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"${target}-${variant}-sd" = sd;
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} // (
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if builtins.elem target fsblTargets
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then {
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"${targetVariantStr}-fsbl-sd" = fsbl-sd;
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"${target}-${variant}-fsbl-sd" = fsbl-sd;
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}
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else {}
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);
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@ -366,7 +365,7 @@
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(board-package-set { target = "kasli_soc"; variant = "demo"; json = ./demo.json; }) //
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(board-package-set { target = "kasli_soc"; variant = "master"; json = ./kasli-soc-master.json; }) //
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(board-package-set { target = "kasli_soc"; variant = "satellite"; json = ./kasli-soc-satellite.json; }) //
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(board-package-set { target = "ebaz4205"; });
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(board-package-set { target = "ebaz4205"; variant = "base"; });
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hydraJobs = packages.x86_64-linux // { inherit zc706-hitl-tests; inherit gateware-sim; inherit fmt-check; };
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@ -212,6 +212,14 @@ class EBAZ4205(SoCCore):
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self.csr_devices.append("rtio_analyzer")
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class BASE(EBAZ4205):
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def __init__(self, rtio_clk, acpki):
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EBAZ4205.__init__(self, rtio_clk, acpki)
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VARIANTS = {cls.__name__.lower(): cls for cls in [BASE]}
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ port to the EBAZ4205 control card of Ebit E9+ BTC miner"
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@ -232,11 +240,25 @@ def main():
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)
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parser.add_argument("--rtio-clk", default=125e6, help="RTIO Clock Frequency (Hz)")
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parser.add_argument(
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"--acpki", default=False, action="store_true", help="enable ACPKI"
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"-V",
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"--variant",
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default="base",
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help="variant: " "[acpki_]base" "(default: %(default)s)",
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)
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args = parser.parse_args()
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soc = EBAZ4205(rtio_clk=int(args.rtio_clk), acpki=args.acpki)
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rtio_clk = int(args.rtio_clk)
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variant = args.variant.lower()
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acpki = variant.startswith("acpki_")
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if acpki:
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variant = variant[6:]
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try:
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cls = VARIANTS[variant]
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except KeyError:
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raise SystemExit("Invalid variant (-V/--variant)")
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soc = cls(rtio_clk=rtio_clk, acpki=acpki)
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soc.finalize()
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if args.r is not None:
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