forked from M-Labs/artiq-zynq
Remove 150 MHz option from set_fclk0_freq
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@ -425,14 +425,6 @@ fn set_fclk0_freq(clk: RtioClock, cfg: &Config) {
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target_freq = 125_000_000;
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target_freq = 125_000_000;
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divisor0 = 8;
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divisor0 = 8;
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}
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}
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RtioClock::Int_150 => {
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target_freq = 150_000_000;
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divisor0 = 7; // Closest approximation to 150 MHz
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warn!(
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"Closest achievable FCLK0 frequency for RTIO Clock 150 MHz is {:.2} MHz (divider 7).",
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io_pll_freq as f64 / divisor0 as f64
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);
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}
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_ => {
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_ => {
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warn!("Unsupported RTIO Clock: '{:?}'", clk);
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warn!("Unsupported RTIO Clock: '{:?}'", clk);
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return;
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return;
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@ -479,7 +471,7 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
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#[cfg(feature = "target_ebaz4205")]
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#[cfg(feature = "target_ebaz4205")]
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{
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{
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match clk {
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match clk {
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RtioClock::Int_100 | RtioClock::Int_125 | RtioClock::Int_150 => {
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RtioClock::Int_100 | RtioClock::Int_125 => {
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set_fclk0_freq(clk, cfg);
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set_fclk0_freq(clk, cfg);
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}
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}
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_ => {} // Not set for external clocks
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_ => {} // Not set for external clocks
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