forked from M-Labs/artiq-zynq
Add temporary gateware
This commit is contained in:
parent
6937059a10
commit
601957ea32
402
src/gateware/ebaz4205.py
Executable file
402
src/gateware/ebaz4205.py
Executable file
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#!/usr/bin/env python
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import argparse
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from operator import itemgetter
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from migen import *
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from migen.build.platforms import ebaz4205
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from migen.build.generic_platform import Pins, Subsignal, IOStandard, Misc
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from migen_axi.integration.soc_core import SoCCore
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from misoc.interconnect.csr import *
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import (
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ttl_simple,
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dds, # Need to create module for AD9834
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)
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from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
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import dma
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import analyzer
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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# Added while Migen PR gets lands...
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from migen.build.xilinx import XilinxPlatform
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_io = [
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# Green and Red LEDs
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("user_led", 0, Pins("W13"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("W14"), IOStandard("LVCMOS33")),
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# Push Buttons
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("user_btn", 0, Pins("A17"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("A14"), IOStandard("LVCMOS33")),
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# UART
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(
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"serial",
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0,
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Subsignal("tx", Pins("A16")),
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Subsignal("rx", Pins("F15")),
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IOStandard("LVCMOS33"),
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),
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# SD Card
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(
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"sdcard",
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0,
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Subsignal("detect", Pins("A12"), Misc("PULLUP True")),
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Subsignal("data", Pins("E12 A9 F13 B15")),
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Subsignal("cmd", Pins("C17")),
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Subsignal("clk", Pins("D14")),
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Subsignal("cd", Pins("B15")),
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IOStandard("LVCMOS33"),
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Misc("SLEW=FAST"),
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),
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# NAND Flash
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(
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"nandflash",
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0,
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Subsignal("nand_data", Pins("A6 A5 B7 E8 B5 E9 C6 D9")),
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Subsignal("nand_ce", Pins("E6")),
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Subsignal("nand_re", Pins("D5")),
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Subsignal("nand_we", Pins("D6")),
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Subsignal("nand_ale", Pins("B8")),
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Subsignal("nand_cle", Pins("D8")),
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Subsignal("nand_rb", Pins("C5")),
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IOStandard("LVCMOS33"),
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),
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# ETH PHY
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(
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"gmii",
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0,
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Subsignal("rxd", Pins("Y16 V16 V17 Y17")),
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Subsignal("txd", Pins("W18 Y18 V18 Y19")),
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Subsignal("rx_clk", Pins("U14")),
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Subsignal("tx_clk", Pins("U15")),
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Subsignal("rx_dv", Pins("W16")),
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Subsignal("tx_en", Pins("W19")),
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IOStandard("LVCMOS33"),
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),
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(
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"mdio",
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0,
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Subsignal("mdio", Pins("Y14")),
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Subsignal("mdc", Pins("W15")),
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IOStandard("LVCMOS33"),
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),
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]
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# DATA1-3 2x10 2.0mm Pitch
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# J3 and J5 1x4 2.54mm Pitch
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_connectors = [
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(
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"DATA1",
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{
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"DATA1-5": "A20",
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"DATA1-6": "H16",
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"DATA1-7": "B19",
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"DATA1-8": "B20",
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"DATA1-9": "C20",
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"DATA1-11": "H17",
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"DATA1-13": "D20",
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"DATA1-14": "D18",
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"DATA1-15": "H18",
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"DATA1-16": "D19",
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"DATA1-17": "F20",
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"DATA1-18": "E19",
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"DATA1-19": "F19",
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"DATA1-20": "K17",
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},
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),
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(
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"DATA2",
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{
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"DATA2-5": "G20",
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"DATA2-6": "J18",
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"DATA2-7": "G19",
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"DATA2-8": "H20",
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"DATA2-9": "J19",
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"DATA2-11": "K18",
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"DATA2-13": "K19",
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"DATA2-14": "J20",
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"DATA2-15": "L16",
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"DATA2-16": "L19",
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"DATA2-17": "M18",
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"DATA2-18": "L20",
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"DATA2-19": "M20",
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"DATA2-20": "L17",
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},
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),
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(
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"DATA3",
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{
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"DATA3-5": "M19",
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"DATA3-6": "N20",
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"DATA3-7": "P18",
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"DATA3-8": "M17",
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"DATA3-9": "N17",
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"DATA3-11": "P20",
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"DATA3-13": "R18",
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"DATA3-14": "R19",
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"DATA3-15": "P19",
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"DATA3-16": "T20",
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"DATA3-17": "U20",
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"DATA3-18": "T19",
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"DATA3-19": "V20",
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"DATA3-20": "U19",
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},
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),
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(
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"J3",
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{
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"J3-4-TX": "U12",
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"J3-3-RX": "V13",
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},
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"J5",
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{
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"J5-4-TX": "V12",
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"J5-3-RX": "V15",
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},
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),
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]
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class Platform(XilinxPlatform):
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def __init__(self):
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XilinxPlatform.__init__(
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self, "xc7z010-clg400-1", _io, _connectors, toolchain="vivado"
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)
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__all__ = ["Platform"]
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_ps = [
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(
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"ps",
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0,
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Subsignal("clk", Pins("E7"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
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Subsignal("por_b", Pins("C7"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
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Subsignal("srst_b", Pins("B10"), IOStandard("LVCMOS18"), Misc("SLEW=FAST")),
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)
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]
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_ddr = [
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(
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"ddr",
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0,
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Subsignal(
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"a",
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Pins("N2 K2 M3 K3 M4 L1 L4 K4 K1 J4 F5 G4 E4 D4 F4"),
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IOStandard("SSTL15"),
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),
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Subsignal("ba", Pins("L5 R4 J5"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("P5"), IOStandard("SSTL15")),
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Subsignal("cke", Pins("N3"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("N1"), IOStandard("SSTL15")),
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Subsignal("ck_n", Pins("M2"), IOStandard("DIFF_SSTL15"), Misc("SLEW=FAST")),
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Subsignal("ck_p", Pins("L2"), IOStandard("DIFF_SSTL15"), Misc("SLEW=FAST")),
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# Pins "T1 Y1" not connected
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Subsignal("dm", Pins("A1 F1"), IOStandard("SSTL15_T_DCI"), Misc("SLEW=FAST")),
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Subsignal(
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"dq",
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Pins("C3 B3 A2 A4 D3 D1 C1 E1 E2 E3 G3 H3 J3 H2 H1 J1"),
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# Pins "P1 P3 R3 R1 T4 U4 U2 U3 V1 Y3 W1 Y4 Y2 W3 V2 V3" not connected
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IOStandard("SSTL15_T_DCI"),
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Misc("SLEW=FAST"),
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),
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Subsignal(
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"dqs_n",
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Pins("B2 F2"), # Pins "T2 W4" not connected
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IOStandard("DIFF_SSTL15_T_DCI"),
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Misc("SLEW=FAST"),
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),
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Subsignal(
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"dqs_p",
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Pins("C2 G2"), # Pins "R2 W5" not connected
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IOStandard("DIFF_SSTL15_T_DCI"),
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Misc("SLEW=FAST"),
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),
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Subsignal("vrn", Pins("G5"), IOStandard("SSTL15_T_DCI"), Misc("SLEW=FAST")),
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Subsignal("vrp", Pins("H5"), IOStandard("SSTL15_T_DCI"), Misc("SLEW=FAST")),
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Subsignal("drst_n", Pins("B4"), IOStandard("SSTL15"), Misc("SLEW=FAST")),
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Subsignal("odt", Pins("N5"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("P4"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("M5"), IOStandard("SSTL15")),
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)
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]
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class EBAZ4205(SoCCore):
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def __init__(self, acpki=False):
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self.acpki = acpki
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# platform = ebaz4205.Platform()
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platform = Platform()
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platform.toolchain.bitstream_commands.extend(
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[
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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]
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)
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platform.add_extension(_ps)
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platform.add_extension(_ddr)
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# FCLK is tied to pin U18
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platform.add_extension(
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[
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("fclk", 0, Pins("U18"), IOStandard("LVCMOS33")),
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]
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)
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gmii = platform.request("gmii")
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platform.add_period_constraint(gmii.rx_clk, 10)
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platform.add_period_constraint(gmii.tx_clk, 10)
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platform.add_platform_command(
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"set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gmii_tx_clk_IBUF]"
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)
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ident = self.__class__.__name__
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if self.acpki:
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ident = "acpki_" + ident
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SoCCore.__init__(
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self,
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platform=platform,
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csr_data_width=32,
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ident=ident,
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)
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fix_serdes_timing_path(platform)
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# When using pd_cd_sys, the default clock coming from fclk.clk[0] is 100 MHz
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self.config["RTIO_FREQUENCY"] = "100"
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platform.add_period_constraint(self.ps7.cd_sys.clk, 10)
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self.comb += [
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self.ps7.enet0.enet.gmii.tx_clk.eq(gmii.tx_clk),
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self.ps7.enet0.enet.gmii.rx_clk.eq(gmii.rx_clk),
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]
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self.clock_domains.cd_eth_rx = ClockDomain(reset_less=False)
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self.clock_domains.cd_eth_tx = ClockDomain(reset_less=False)
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self.comb += [
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ClockSignal("eth_rx").eq(gmii.rx_clk),
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ClockSignal("eth_tx").eq(gmii.tx_clk),
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]
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self.sync.eth_tx += [
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gmii.txd.eq(self.ps7.enet0.enet.gmii.txd),
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gmii.tx_en.eq(self.ps7.enet0.enet.gmii.tx_en),
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]
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self.sync.eth_rx += [
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self.ps7.enet0.enet.gmii.rxd.eq(gmii.rxd),
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self.ps7.enet0.enet.gmii.rx_dv.eq(gmii.rx_dv),
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]
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# FCLK
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fclk = platform.request("fclk")
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self.comb += fclk.eq(self.ps7.fclk.clk[0])
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# MDIO/MDC
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mdio = platform.request("mdio")
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self.comb += [
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mdio.mdc.eq(self.ps7.enet0.enet.mdio.mdc),
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]
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mdio_t = Signal()
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self.comb += mdio_t.eq(~self.ps7.enet0.enet.mdio.t_n)
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self.specials += [
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Instance(
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"IOBUF",
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i_I=self.ps7.enet0.enet.mdio.o,
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io_IO=mdio.mdio,
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o_O=self.ps7.enet0.enet.mdio.i,
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i_T=mdio_t,
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)
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]
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self.rtio_channels = []
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for i in (0, 1):
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print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
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user_led = self.platform.request("user_led", i)
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phy = ttl_simple.Output(user_led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels)
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self.csr_devices.append("rtio_core")
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if self.acpki:
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import acpki
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self.config["KI_IMPL"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(
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self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o,
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)
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self.csr_devices.append("rtio")
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else:
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self.config["KI_IMPL"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
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self.csr_devices.append("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri],
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enable_routing=True,
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)
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self.csr_devices.append("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = analyzer.Analyzer(
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self.rtio_tsc, self.rtio_core.cri, self.ps7.s_axi_hp1
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)
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self.csr_devices.append("rtio_analyzer")
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ port to the EBAZ4205 control card of Ebit E9+ BTC miner"
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)
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parser.add_argument(
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"-r", default=None, help="build Rust interface into the specified file"
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)
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parser.add_argument(
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"-m", default=None, help="build Rust memory interface into the specified file"
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)
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parser.add_argument(
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"-c",
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default=None,
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help="build Rust compiler configuration into the specified file",
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)
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parser.add_argument(
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"-g", default=None, help="build gateware into the specified directory"
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)
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parser.add_argument(
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"--acpki", default=False, action="store_true", help="enable ACPKI"
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)
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args = parser.parse_args()
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soc = EBAZ4205()
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soc.finalize()
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if args.r is not None:
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write_csr_file(soc, args.r)
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if args.m is not None:
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write_mem_file(soc, args.m)
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if args.c is not None:
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write_rustc_cfg_file(soc, args.c)
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if args.g is not None:
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soc.build(build_dir=args.g)
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if __name__ == "__main__":
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main()
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