forked from M-Labs/artiq-zynq
Make TTLs InOut in gateware
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@ -5,7 +5,7 @@ import argparse
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import analyzer
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import analyzer
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import dma
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import dma
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from artiq.gateware import rtio
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import dds, spi2, ttl_simple
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from artiq.gateware.rtio.phy import spi2, ttl_simple
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from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
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from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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from migen import *
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from migen import *
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@ -195,7 +195,7 @@ class EBAZ4205(SoCCore):
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for i in range(14):
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for i in range(14):
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print("TTL at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
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print("TTL at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
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ttl = self.platform.request("ttl", i)
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ttl = self.platform.request("ttl", i)
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phy = ttl_simple.Output(ttl)
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phy = ttl_simple.InOut(ttl)
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self.submodules += phy
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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