diff --git a/src/gateware/ebaz4205.py b/src/gateware/ebaz4205.py
index bc593c9..d64d2e1 100644
--- a/src/gateware/ebaz4205.py
+++ b/src/gateware/ebaz4205.py
@@ -5,7 +5,7 @@ import argparse
 import analyzer
 import dma
 from artiq.gateware import rtio
-from artiq.gateware.rtio.phy import dds, spi2, ttl_simple
+from artiq.gateware.rtio.phy import spi2, ttl_simple
 from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
 from config import write_csr_file, write_mem_file, write_rustc_cfg_file
 from migen import *
@@ -195,7 +195,7 @@ class EBAZ4205(SoCCore):
         for i in range(14):
             print("TTL at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
             ttl = self.platform.request("ttl", i)
-            phy = ttl_simple.Output(ttl)
+            phy = ttl_simple.InOut(ttl)
             self.submodules += phy
             self.rtio_channels.append(rtio.Channel.from_phy(phy))