newell/artiq-zynq
1
0
Fork 0
forked from M-Labs/artiq-zynq
Code Pull Requests Activity

Make TTLs InOut in gateware

Browse Source
This commit is contained in:
newell 2024-11-14 13:24:56 -08:00
parent 265c52bc2a
commit 3f2d111abb
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/gateware/ebaz4205.py
View File

@ -5,7 +5,7 @@ import argparse
import analyzer
import dma
from artiq.gateware import rtio
from artiq.gateware.rtio.phy import dds, spi2, ttl_simple
from artiq.gateware.rtio.phy import spi2, ttl_simple
from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
from config import write_csr_file, write_mem_file, write_rustc_cfg_file
from migen import *
@ -195,7 +195,7 @@ class EBAZ4205(SoCCore):
for i in range(14):
print("TTL at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
ttl = self.platform.request("ttl", i)
phy = ttl_simple.Output(ttl)
phy = ttl_simple.InOut(ttl)
self.submodules += phy
self.rtio_channels.append(rtio.Channel.from_phy(phy))