forked from M-Labs/artiq-zynq
Remove incorrect pmod reference
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parent
1a3af696af
commit
0f1945f4ca
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@ -79,9 +79,9 @@ _i2c = [
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)
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)
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]
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]
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_pmod_spi = [
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_spi = [
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(
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(
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"pmod_spi",
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"spi",
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0,
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0,
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Subsignal("clk", Pins("V20")),
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Subsignal("clk", Pins("V20")),
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Subsignal("mosi", Pins("U20")),
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Subsignal("mosi", Pins("U20")),
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@ -104,7 +104,7 @@ class EBAZ4205(SoCCore):
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platform.add_extension(_ps)
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platform.add_extension(_ps)
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platform.add_extension(_ddr)
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platform.add_extension(_ddr)
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platform.add_extension(_i2c)
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platform.add_extension(_i2c)
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platform.add_extension(_pmod_spi)
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platform.add_extension(_spi)
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gmii = platform.request("gmii")
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gmii = platform.request("gmii")
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platform.add_period_constraint(gmii.rx_clk, 10)
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platform.add_period_constraint(gmii.rx_clk, 10)
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@ -181,7 +181,7 @@ class EBAZ4205(SoCCore):
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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print("SPI at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
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print("SPI at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
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spi_phy = spi2.SPIMaster(platform.request("pmod_spi"))
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spi_phy = spi2.SPIMaster(platform.request("spi"))
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self.submodules += spi_phy
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self.submodules += spi_phy
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self.rtio_channels.append(rtio.Channel.from_phy(spi_phy, ififo_depth=4))
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self.rtio_channels.append(rtio.Channel.from_phy(spi_phy, ififo_depth=4))
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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