mwojcik

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• Joined on 2021-07-22

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mwojcik pushed to master at M-Labs/artiq-zynq 2021-12-03 19:21:21 +08:00

64fecf09b7 restore kasli-soc satellite variant check

mwojcik created pull request M-Labs/artiq-zynq#155 2021-12-03 12:21:30 +08:00

Support for DRTIO 100MHz

mwojcik pushed to drtio_100mhz at mwojcik/artiq-zynq 2021-12-03 11:18:29 +08:00

fff5e8fe1e kasli_soc: custom (incl 100mhz) rtio_freq support

mwojcik pushed to drtio_100mhz at mwojcik/artiq-zynq 2021-12-01 16:25:04 +08:00

f1b1a8303a drtio: * add 100mhz variants,

015ec8e88f restore ultrascale

c43d5ba492 Merge branch 'master' into drtio_100mhz

e045837b67 zc706: not actually ultrascale

ada3f2e704 drtio: reading still needs work buffer after all

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mwojcik pushed to master at M-Labs/artiq-zynq 2021-11-29 12:48:50 +08:00

e045837b67 zc706: not actually ultrascale

mwojcik created pull request M-Labs/artiq-zynq#154 2021-11-29 12:33:12 +08:00

drtio: reading still needs work buffer after all

mwojcik pushed to drtio_sat_fix at mwojcik/artiq-zynq 2021-11-29 12:27:32 +08:00

e8a18a7977 drtio: reading still needs work buffer after all

mwojcik created branch drtio_sat_fix in mwojcik/artiq-zynq 2021-11-29 12:27:32 +08:00

mwojcik created branch drtio_100mhz in mwojcik/artiq-zynq 2021-11-26 13:29:10 +08:00

mwojcik pushed to drtio_100mhz at mwojcik/artiq-zynq 2021-11-26 13:29:10 +08:00

5f247bb09e add switch for drtio 100mhz clock

mwojcik pushed to clock_input_improv at mwojcik/artiq-zynq 2021-11-25 16:39:00 +08:00

ee3b1715cb rtio_clock: cfg uses default now, info->warn

mwojcik created pull request M-Labs/artiq-zynq#153 2021-11-24 12:33:06 +08:00

drtio crc fix

mwojcik pushed to drtio_checksum_fix at mwojcik/artiq-zynq 2021-11-24 12:12:55 +08:00

e8db2a4b49 drtio: crc from mainline, removed byte swap

416dacf56b drtio: crc from mainline, removed byte swap

Compare 2 commits »

mwojcik pushed to drtio_checksum_fix at mwojcik/artiq-zynq 2021-11-24 12:06:59 +08:00

416dacf56b drtio: crc from mainline, removed byte swap

mwojcik created branch drtio_checksum_fix in mwojcik/artiq-zynq 2021-11-24 12:06:59 +08:00

mwojcik commented on issue M-Labs/artiq-zynq#143 2021-11-22 16:46:22 +08:00

add MGT_SMA DRTIO link

The link itself is confirmed working - had to disconnect the SFP and change the order in the gateware file (note: having both SMA and SFP connected at the same time seems to be confusing for both…

mwojcik commented on pull request M-Labs/artiq-zynq#152 2021-10-29 14:24:26 +08:00

Clock input settings improvements

Ah, I thought it goes through Si5324 on DRTIO variants - Standalone of course wouldn't work. But yeah, getting DRP to work would be more work than it's worth.

mwojcik commented on pull request M-Labs/artiq-zynq#152 2021-10-29 10:44:54 +08:00

Clock input settings improvements

I would add that for debugging purposes, it's useful for us to have int_100 available as well, so that we can do bench tests and verify performance at 100 MHz DRTIO clock without having to hook…

mwojcik pushed to clock_input_improv at mwojcik/artiq-zynq 2021-10-29 10:33:09 +08:00

07410afe83 rtio_clocking: remove unrelated comment

mwojcik pushed to clock_input_improv at mwojcik/artiq-zynq 2021-10-29 09:56:49 +08:00

a82e7a332b gateware: kasli_soc: fix missing si5324 support