• Joined on 2021-07-22
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mwojcik pushed to drtio_port at M-Labs/artiq-zynq

  • 59cf4bc689 libboard_zynq: fully modified to work with core_io

2021-08-27 21:16:18 +08:00

mwojcik pushed to drtio_port at M-Labs/artiq-zynq

  • 581f6c6b4e libboard_artiq: tried moving drtio to io::proto

2021-08-27 20:44:59 +08:00

mwojcik pushed to drtio_port at M-Labs/artiq-zynq

  • e0516eeda9 libio: removed custom read/write, moved to core_io

2021-08-27 19:12:23 +08:00

mwojcik pushed to drtio_port at M-Labs/artiq-zynq

2021-08-26 21:20:40 +08:00

mwojcik pushed to drtio_port at M-Labs/artiq-zynq

  • cb3f0a404c libio: read/write traits from libio not core_io

2021-08-26 20:59:09 +08:00

mwojcik pushed to drtio_port at M-Labs/artiq-zynq

2021-08-26 19:16:55 +08:00

mwojcik pushed to drtio_port at M-Labs/artiq-zynq

2021-08-26 18:54:24 +08:00

mwojcik pushed to drtio_port at M-Labs/artiq-zynq

  • 39d522e1a7 drtioaux_proto: removed failure, need to fix traits

2021-08-25 19:03:59 +08:00

mwojcik pushed to drtio_port at M-Labs/artiq-zynq

  • a8a2da575b libboard_artiq: added mem.rs, yet to fix drtioaux

2021-08-24 20:11:35 +08:00

mwojcik pushed to drtio_port at M-Labs/artiq-zynq

  • 37eb4669fb makefile: satman support, separated from runtime

2021-08-24 19:57:15 +08:00

mwojcik pushed to drtio_port at M-Labs/artiq-zynq

2021-08-24 19:51:42 +08:00

mwojcik created pull request M-Labs/nix-scripts#65

updated migen-axi dependency to 1f94ee0

2021-08-24 19:32:05 +08:00

mwojcik created branch migen-axi-1f94ee0 in M-Labs/nix-scripts

2021-08-24 19:31:49 +08:00

mwojcik pushed to migen-axi-1f94ee0 at M-Labs/nix-scripts

  • 495dc7ee4e updated migen-axi dependency to 1f94ee0

2021-08-24 19:31:49 +08:00

mwojcik pushed to drtio_port at M-Labs/artiq-zynq

  • 1358c8bfe9 zc706 gateware: base class for drtio is SoCCore

2021-08-24 18:01:11 +08:00

mwojcik pushed to drtio_port at M-Labs/artiq-zynq

2021-08-20 21:14:05 +08:00

mwojcik pushed to drtio_port at M-Labs/artiq-zynq

2021-08-18 18:36:22 +08:00

mwojcik pushed to drtio_port at M-Labs/artiq-zynq

  • 7b868e1c9d few fixes, typos and missed unnecessary statements

2021-08-17 19:16:06 +08:00

mwojcik pushed to drtio_port at M-Labs/artiq-zynq

  • 61f81cec47 sram: redesigned write FSM. removed unused signals

2021-08-17 17:10:12 +08:00

mwojcik pushed to drtio_port at M-Labs/artiq-zynq

  • 3e1d14ff38 replaced increment logic with ready Incr module

2021-08-16 21:33:55 +08:00