• Joined on 2021-07-22
mwojcik created branch drtio_libio in mwojcik/artiq-zynq 2021-10-05 15:45:41 +08:00
mwojcik pushed to drtio_libio at mwojcik/artiq-zynq 2021-10-05 15:45:41 +08:00
23bb185644 added libio from drtio port
mwojcik created branch drtio_libboard in mwojcik/artiq-zynq 2021-10-05 15:42:50 +08:00
mwojcik pushed to drtio_libboard at mwojcik/artiq-zynq 2021-10-05 15:42:50 +08:00
f1bf6b1108 copied libboard_artiq from drtio
mwojcik created branch drtio_gateware in mwojcik/artiq-zynq 2021-10-05 14:42:06 +08:00
mwojcik pushed to drtio_gateware at mwojcik/artiq-zynq 2021-10-05 14:42:06 +08:00
49bbee88bc added missing aux_controller file
1de5e2039f moved gateware files from drtio port
Compare 2 commits »
mwojcik created repository mwojcik/artiq-zynq 2021-10-04 20:15:18 +08:00
mwojcik pushed to drtio_port at M-Labs/artiq-zynq 2021-10-04 18:55:54 +08:00
c3491ed6cd Merge branch 'master' into drtio_port
35250b3f56 libdyld: fixed symbol relocation
2ed2ffe417 update dependencies
Compare 3 commits »
mwojcik pushed to drtio_port at M-Labs/artiq-zynq 2021-10-04 14:53:43 +08:00
db1c9d336e aux_controller: fix class parent
mwojcik pushed to drtio_port at M-Labs/artiq-zynq 2021-10-01 21:37:04 +08:00
b9da4c27fe one more unnecessary comment gone
mwojcik pushed to drtio_port at M-Labs/artiq-zynq 2021-10-01 21:35:05 +08:00
38088cea87 cleanup, less unnecessary comments and dup code
mwojcik pushed to drtio_port at M-Labs/artiq-zynq 2021-10-01 21:08:05 +08:00
26483e852c libboard_artiq: fixes for siphaser, cleanup
mwojcik pushed to drtio_port at M-Labs/artiq-zynq 2021-10-01 18:53:35 +08:00
758adf0495 drtioaux: created async version
mwojcik pushed to drtio_port at M-Labs/artiq-zynq 2021-10-01 17:50:01 +08:00
2caa48f24b libboard_artiq: changed edition to 2018 for async
mwojcik pushed to drtio_port at M-Labs/artiq-zynq 2021-09-30 19:32:25 +08:00
5f06db8787 drtio: swap byte order, add work buffer, comm ok
mwojcik pushed to drtio_port at M-Labs/artiq-zynq 2021-09-29 20:01:12 +08:00
f23c6cdb18 aux_controller: fix axi sram data paths
mwojcik pushed to drtio_port at M-Labs/artiq-zynq 2021-09-29 17:50:58 +08:00
8ab2b3f299 aux_controller: connect r/w/b lanes to axi bus
mwojcik pushed to drtio_port at M-Labs/artiq-zynq 2021-09-27 21:50:24 +08:00
b9f0bb3899 runtime: enable target feature for libboard_artiq
mwojcik pushed to drtio_port at M-Labs/artiq-zynq 2021-09-27 21:06:37 +08:00
f897c41d2b master: fix lifetime of drtio variables
mwojcik pushed to drtio_port at M-Labs/artiq-zynq 2021-09-24 20:15:36 +08:00
6dbd817d3e master: runtime fixes per compiler's requests